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nuc126 aug . 08 , 201 8 page 1 of 140 rev 1 .0 4 nuc126 series datasheet arm cortex ? - m 32 - bit microcontroller numicro ? family nuc126 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
nuc126 aug . 08 , 201 8 page 2 of 140 rev 1 .0 4 nuc126 series datasheet table of contents 1 general description ................................ ................................ ................. 8 1.1 key feature and application ................................ ................................ ......................... 9 2 features ................................ ................................ ................................ ....... 10 2.1 numicro ? nuc126 features ................................ ................................ ....................... 10 3 abbreviations ................................ ................................ ............................ 18 3.1 abbreviations ................................ ................................ ................................ .............. 18 4 parts information li st and pin configura tion ............................ 20 4.1 numicro ? nuc126 selection guide ................................ ................................ ........... 20 4.1.1 numicro ? nuc126 naming rule ................................ ................................ ................... 20 4.1.2 numicro ? nuc126 usb series (m452 compatible) selection guide ............................ 21 4.2 pin configuration ................................ ................................ ................................ ........ 22 4.2.1 numicro ? nuc126 usb series qfn 48 pin diagram ................................ .................... 22 4.2.2 numicro ? nuc126 usb series lqfp48 pin diagram ................................ ................... 23 4.2.3 numicro ? nuc126 usb series lqfp64 pin diagram ................................ ................... 24 4.2.4 numicro ? nuc126 usb series lqfp100 pin diagram ................................ ................. 25 4.3 pin description ................................ ................................ ................................ ............ 26 4.3.1 nuc126 usb series pin description ................................ ................................ ............. 26 4.3.2 gpio multi - function pin summary ................................ ................................ ................. 41 5 block diagram ................................ ................................ ........................... 53 5.1 numicro ? nuc126 block diagram ................................ ................................ ............. 53 6 functional descripti on ................................ ................................ ......... 54 6.1 arm ? cortex ? - m0 core ................................ ................................ .............................. 54 6.2 system manager ................................ ................................ ................................ ......... 56 6.2.1 overview ................................ ................................ ................................ ........................ 56 6.2.2 system r eset ................................ ................................ ................................ ................. 56 6.2.3 power modes and wake - up sources ................................ ................................ ............. 63 6.2.4 system power distribution ................................ ................................ ............................. 66 6.2.5 system memory map ................................ ................................ ................................ ..... 68 6.2.6 sram memory orginization ................................ ................................ ........................... 70 6.2.7 register lock ................................ ................................ ................................ ................. 71 6.2.8 auto trim ................................ ................................ ................................ ....................... 71 6.2.9 uart1_ txd modulation with pwm ................................ ................................ ............... 72 6.2.10 voltage detector ( vdet ) ................................ ................................ ............................... 73 6.2.11 system timer (systick) ................................ ................................ ................................ . 74 6.2.12 nested vectored interrupt controller (nvic) ................................ ................................ .. 75 6.3 clock controller ................................ ................................ ................................ .......... 78 6.3.1 overview ................................ ................................ ................................ ........................ 78 6.3.2 system c lock and systick clock ................................ ................................ ................... 81 6.3.3 peripherals clock ................................ ................................ ................................ ........... 82 6.3.4 power - down mode clock ................................ ................................ ............................... 83 6.3.5 clock output ................................ ................................ ................................ .................. 83
nuc126 aug . 08 , 201 8 page 3 of 140 rev 1 .0 4 nuc126 series datasheet 6.4 flash memeory controller (fmc) ................................ ................................ ............... 85 6.4.1 overview ................................ ................................ ................................ ........................ 85 6.4.2 features ................................ ................................ ................................ ......................... 85 6.5 analog comparator controller (acmp) ................................ ................................ ...... 86 6.5.1 overview ................................ ................................ ................................ ........................ 86 6.5.2 features ................................ ................................ ................................ ......................... 86 6.6 analog - to - digital converter (adc) ................................ ................................ ............. 87 6.6.1 overview ................................ ................................ ................................ ........................ 87 6.6.2 features ................................ ................................ ................................ ......................... 87 6.7 crc contro ller (crc) ................................ ................................ ................................ 88 6.7.1 overview ................................ ................................ ................................ ........................ 88 6.7.2 features ................................ ................................ ................................ ......................... 88 6.8 external bus interface (ebi) ................................ ................................ ....................... 89 6.8.1 overview ................................ ................................ ................................ ........................ 89 6.8.2 features ................................ ................................ ................................ ......................... 89 6.9 general purpose i/o (gpio) ................................ ................................ ...................... 90 6.9.1 overview ................................ ................................ ................................ ........................ 90 6.9.2 features ................................ ................................ ................................ ......................... 90 6.10 hardware divider (hdiv) ................................ ................................ ............................ 91 6.10.1 overview ................................ ................................ ................................ ........................ 91 6.10.2 featu res ................................ ................................ ................................ ......................... 91 6.10.3 blcok d iagram ................................ ................................ ................................ ................ 91 6.11 i 2 c serial interface controller (i 2 c) ................................ ................................ ............. 92 6.11.1 overview ................................ ................................ ................................ ........................ 92 6.11.2 features ................................ ................................ ................................ ......................... 92 6.12 pdma co ntroller (pdma) ................................ ................................ ........................... 93 6.12.1 overview ................................ ................................ ................................ ........................ 93 6.12.2 features ................................ ................................ ................................ ......................... 93 6.13 pwm gen erator and capture timer (pwm) ................................ .............................. 94 6.13.1 overview ................................ ................................ ................................ ........................ 94 6.13.2 features ................................ ................................ ................................ ......................... 94 6.14 real time clock (rtc) ................................ ................................ ............................... 96 6.14.1 overview ................................ ................................ ................................ ........................ 96 6.14.2 features ................................ ................................ ................................ ......................... 96 6.15 smart card host interface (sc) ................................ ................................ .................. 97 6.15.1 overview ................................ ................................ ................................ ........................ 97 6.15.2 features ................................ ................................ ................................ ......................... 97 6.16 serial peripheral interface (spi) ................................ ................................ ................. 98 6.16.1 overview ................................ ................................ ................................ ........................ 98 6.16.2 featu res ................................ ................................ ................................ ......................... 98 6.17 timer controller (tmr) ................................ ................................ ............................... 99 6.17.1 overview ................................ ................................ ................................ ........................ 99 6.17.2 featu res ................................ ................................ ................................ ......................... 99 6.18 usb device controller (usbd) ................................ ................................ ................ 101
nuc126 aug . 08 , 201 8 page 4 of 140 rev 1 .0 4 nuc126 series datasheet 6.18.1 overview ................................ ................................ ................................ ...................... 101 6.18.2 features ................................ ................................ ................................ ....................... 101 6.19 usci C universal serial control interface controller ................................ ................ 102 6.19.1 overview ................................ ................................ ................................ ...................... 102 6.19.2 features ................................ ................................ ................................ ....................... 102 6.20 usci C uart m ode ................................ ................................ ................................ . 103 6.20.1 overview ................................ ................................ ................................ ...................... 103 6.20.2 featu res ................................ ................................ ................................ ....................... 103 6.21 usci C spi m ode ................................ ................................ ................................ ..... 104 6.21.1 overview ................................ ................................ ................................ ...................... 104 6.21.2 features ................................ ................................ ................................ ....................... 104 6.22 usci C i 2 c m ode ................................ ................................ ................................ ...... 106 6.22.1 overview ................................ ................................ ................................ ...................... 106 6.22.2 featu res ................................ ................................ ................................ ....................... 106 6.23 uart interface controller (uart) ................................ ................................ ........... 107 6.23.1 overview ................................ ................................ ................................ ...................... 107 6.23.2 featu res ................................ ................................ ................................ ....................... 107 6.24 watchdog timer (wdt) ................................ ................................ ............................ 108 6.24.1 overview ................................ ................................ ................................ ...................... 108 6.24.2 features ................................ ................................ ................................ ....................... 108 6.24.3 clock control ................................ ................................ ................................ ............... 108 6.25 window watchdog timer (wwdt) ................................ ................................ ........... 109 6.25.1 overview ................................ ................................ ................................ ...................... 109 6.25.2 featu res ................................ ................................ ................................ ....................... 109 6.25.3 clock control ................................ ................................ ................................ ............... 109 7 application circuit ................................ ................................ ................ 110 8 electrical character istics ................................ .............................. 111 8.1 absolute maximum ratings ................................ ................................ ...................... 111 8.2 dc electrical characteristics ................................ ................................ .................... 112 8.3 ac electrical characteristics ................................ ................................ .................... 120 8.3.1 external 4~24 mhz high speed crystal (hxt) input clock ................................ ......... 120 8.3.2 external 4~24 mhz high speed crystal (hxt) oscillator ................................ ............ 120 8.3.3 external 32.768 khz low speed crystal (lxt) input clock ................................ ......... 121 8.3.4 external 32.768 khz low speed crystal (lxt) input clock ................................ ......... 122 8.3.5 internal 48 mhz high speed rc oscillator (hirc48) ................................ .................. 123 8.3.6 internal 22.1184 mhz high speed rc oscillator (hirc) ................................ ............. 123 8.3.7 internal 10 khz low speed rc oscillator (lirc) ................................ ........................ 123 8.4 analog characteristics ................................ ................................ .............................. 125 8.4.1 ldo ................................ ................................ ................................ .............................. 125 8.4.2 temperature sensor ................................ ................................ ................................ .... 125 8.4.3 internal voltage reference (int_v ref ) ................................ ................................ .......... 125 8.4.4 power - on reset ................................ ................................ ................................ ........... 126 8.4.5 low - voltage reset ................................ ................................ ................................ ....... 126 8.4.6 brown - out detector ................................ ................................ ................................ ...... 126
nuc126 aug . 08 , 201 8 page 5 of 140 rev 1 .0 4 nuc126 series datasheet 8.4.7 12 - bit adc ................................ ................................ ................................ ................... 127 8.4.8 anal og comparator ................................ ................................ ................................ ...... 129 8.4.9 usb phy ................................ ................................ ................................ ..................... 130 8.5 flash dc electrical characteris ................................ ................................ ................ 131 8.6 i2c dynamic characteristics ................................ ................................ .................... 132 8.7 spi dynamic characteristics ................................ ................................ .................... 133 8.7.1 dynamic characteristics of data input and output pin ................................ ................ 133 9 package dimensions ................................ ................................ .............. 135 9.1 lqfp 100l (14x14x1.4 mm footprint 2.0 mm) ................................ ......................... 135 9.2 lqfp 64l (7x7x1.4 mm footprint 2.0 mm) ................................ ............................... 136 9.3 lqfp 48l (7x7x1.4 mm footprint 2.0 mm) ................................ .............................. 137 9.4 qf n 48l (7x7x 0.8 mm) ................................ ................................ ............................ 138 10 revision history ................................ ................................ ...................... 139
nuc126 aug . 08 , 201 8 page 6 of 140 rev 1 .0 4 nuc126 series datasheet list of figures figure 4.2 - 1 numicro ? nuc126 usb series qf n 48 - pin diagram ................................ ............... 22 figure 4.2 - 2 numicro ? nuc126 usb series lqfp 48 - pin diagram ................................ ............. 23 figure 4.2 - 3 numicro ? nuc126 usb series lqfp 64 - pin diagram ................................ ............. 24 figure 4.2 - 4 numicro ? nuc126 usb series lqfp 100 - pin diagram ................................ ........... 25 figure 5.1 - 1 numicro ? nuc126 block diagram ................................ ................................ ............. 53 figure 6.1 - 1 functional block diagram ................................ ................................ .......................... 54 figure 6.2 - 1 system reset sources ................................ ................................ ............................... 57 figure 6.2 - 2 nreset reset waveform ................................ ................................ ......................... 59 figure 6.2 - 3 power - on reset (por) waveform ................................ ................................ ............. 60 figure 6.2 - 4 low voltage reset (lvr) waveform ................................ ................................ ......... 61 figure 6.2 - 5 brown - out detector (bod) waveform ................................ ................................ ....... 62 figure 6.2 - 6 numicro ? nuc126 power mode state machine ................................ ........................ 64 figure 6.2 - 7 numicro ? nuc126 power distribution diagram ................................ ........................ 67 figure 6.2 - 8 sram block diagram ................................ ................................ ................................ 70 figure 6.2 - 9 sram memory organization ................................ ................................ ..................... 71 figure 6.2 - 10 uart1_txd modulated with pwm channel ................................ ........................... 72 figure 6.2 - 11 vdet block diagram ................................ ................................ ............................... 73 figure 6.3 - 1 clock generator block diagram ................................ ................................ ................. 79 figure 6.3 - 2 clock generator global view diagram ................................ ................................ ...... 80 figure 6.3 - 3 system clock block diagram ................................ ................................ ..................... 81 figure 6.3 - 4 hxt stop protect procedure ................................ ................................ ...................... 82 figure 6.3 - 5 systick clock control block diagram ................................ ................................ ....... 82 figure 6.3 - 6 clock source of clock output ................................ ................................ .................... 83 figure 6.3 - 7 clock output block diagram ................................ ................................ ...................... 84 figure 6.10 - 1 hardware divider block diagram ................................ ................................ ............. 91 figure 6.21 - 1 spi master mode application block di agram ................................ ........................ 104 figure 6.21 - 2 spi slave mode application block diagram ................................ .......................... 104 figure 6.22 - 1 i 2 c bus timing ................................ ................................ ................................ ....... 106 figure 6.24 - 1 watchdog timer clock control ................................ ................................ .............. 108 figure 6.25 - 1 wwdt clock control ................................ ................................ ............................. 109 figure 8.3 - 1 typical crystal application circuit ................................ ................................ ............ 121 figure 8.3 - 2 typical crystal application circuit ................................ ................................ ............ 122 figure 8.6 - 1 i 2 c timing diagram ................................ ................................ ................................ .. 132 figure 8.7 - 1 spi master mode timing diagram ................................ ................................ ........... 133 figure 8.7 - 2 spi slave mode timing diagram ................................ ................................ ............. 134
nuc126 aug . 08 , 201 8 page 7 of 140 rev 1 .0 4 nuc126 series datasheet list of tables table 1.1 - 1 key features support table ................................ ................................ ......................... 9 table 3.1 - 1 list of abbreviations ................................ ................................ ................................ .... 19 table 4.3 - 1 nuc126 gpio multi - function table ................................ ................................ ............ 52 table 6.2 - 1 reset value of registers ................................ ................................ ............................. 59 table 6.2 - 2 power mode difference table ................................ ................................ ..................... 63 table 6.2 - 3 clocks in power modes ................................ ................................ .............................. 65 table 6.2 - 4 condition of entering power - down mode again ................................ ......................... 66 table 6.2 - 5 address space assignments for on - chip controllers ................................ ................ 69 table 6.2 - 6 exception model ................................ ................................ ................................ .......... 76 table 6.2 - 7 interrupt number table ................................ ................................ ............................... 77 table 6.3 - 8 clock stable count value table ................................ ................................ ................. 79
nuc126 aug . 08 , 201 8 page 8 of 140 rev 1 .0 4 nuc126 series datasheet 1 general description the numicro ? nuc126 series microcontroller based on the arm ? cortex ? - m0 core operates at up to 72 mhz. with its crystal - less usb 2.0 fs interface, it is able to generate precise frequency required by usb protocol without the need of external crystal. it features adjustable v ddio pins for specific i/o pins with a wide range of voltage from 1.8v to 5.5v for various operating voltages of external components, a unique high - speed pwm with clock frequency up to 144 mhz for precision control, and an integrated hardware divider to speed up the calculation for the control algorithms. apart from that, the nuc126 also integrates sprom (security protection rom) which p rovides a secure code execution area to protect the intelligent property of developers. the nuc126 series is ideal for industrial control, motor control and metering applications. the nuc126 series supports the wide voltage range from 2.5v to 5.5v and temp erature ranging from - 40 to 105 , up to 256 kbytes of flash memory, 20 kbytes of sram, 4 kbytes of isp (in - system programming) rom as well as icp (in - circuit programming) rom and iap (in - application programming) rom in 48 - , 64 - or 100 - pin packages. it als o supports high immunity of 8kv esd (hbm)/4kv eft. it is also equipped with plenty of peripherals such as usb interface, timers, watchdog timers, rtc, pdma, ebi, uart, smart card interface, spi, i2s, i2c, gpio, up to 12 channels of 16 - bit pwm, up to 20 cha nnels of 12 - bit adc, analog comparator, temperature sensor, low voltage reset, brown - out detector, 96 - bit uid (unique identification), and 128 - bit ucid (unique customer identification).
nuc126 aug . 08 , 201 8 page 9 of 140 rev 1 .0 4 nuc126 series datasheet 1.1 key feature and application product line usb usci uart i 2 c spi / i 2 s iso 7 816 pwm ebi pdma adc acmp rtc v bat v ddio nuc126 2.0 fs device 3 3 2 2 2 12 y 5 20 2 y y table 1.1 - 1 key features support table the numicro ? nuc126 series is suitable for a wide range of applications such as: ? industrial automation ? plcs ? inverters ? home automation ? security alarm system ? power metering ? portable data collector ? portable rfid reader ? system supervisors ? smart card reader ? printer ? bar code scanner ? motor control ? digital power
nuc126 aug . 08 , 201 8 page 10 of 140 rev 1 .0 4 nuc126 series datasheet 2 features 2.1 numicro ? nuc126 features ? core C arm ? cortex ? - m 0 core run ning up to 72 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - leve ls of priority C supports programmable mask - able interrupts C serial wire debug supports with 2 watch - points/4 breakpoints ? built - in ldo for wide operating voltage ranged from 2.5v to 5.5v ? flash memory C supports 256/128 kb application rom (aprom) C supports 4 kb flash for loader (ldrom) C supports 2 kb security protection rom (sprom) C supports 12 bytes user configuration block to control system initiation C supports data flash with configurable memory size C supports 2 kb page erase for all embedded flash C supports in - s ystem - programming (isp), in - application - programming (iap) update embedded flash memory C supports crc - 32 checksum calculation function C supports flash all one verification function C hardware external read protection of whole flash memory by security lock bit C s upports 2 - wired icp update through swd/ice interface ? sram memory C 20 k b embedded sram C supports byte - , half - word - and word - access C supports pdma mode ? hardware divider C signed (twos complement) integer calculation C 32 - bit dividend with 16 - bit divisor calculation capacity C 32 - bit quotient and 32 - bit remainder outputs (16 - bit remainder with sign extends to 32 - bit) C divided by zero warning flag C 6 hclk clocks taken for one cycle calculation C write divisor to trigger calculation C waiting for calculation ready automatically when reading quotient and remainder ? pdma (peripheral dma) C supports 5 independent configurable channels for automatic data transfer between memories and peripherals C supports single and burst transfer type C supports normal and scatter - gather tra nsfer modes C supports two types of priorities modes: fixed - priority and round - robin modes C supports byte - , half - word - and word - access C supports incrementing mode for the source and destination address for each channel C supports time - out function for channel 0 and channel 1 C supports software and spi/i2s, uart, usci, usb, adc, pwm and timer request ? clock control
nuc126 aug . 08 , 201 8 page 11 of 140 rev 1 .0 4 nuc126 series datasheet C built - in 22.1184 mhz high speed rc oscillator for system operation (frequency variation < 2% at - 40 o c ~ +105 o c) C built - in 48 mhz internal high speed rc oscillator for usb device operation (frequency variation < 2% at - 40 o c ~ +105 o c) C built - in 10 khz low speed rc oscillator for watchdog timer and wake - up operation C built - in 4~24 mhz high speed crystal oscillator for pre cise timing operation C built - in 32.768 khz low speed crystal oscillator for real time clock C supports pll up to 144 mhz for high resolution pwm operation C supports dynamically calibrating the hirc48 to 48 mhz 0.25% by external 32.768k crystal oscillator (lx t) C supports dynamically calibrating the hirc to 22.1184mhz by external 32.768k crystal oscillator (lxt) C supports clock on - the - fly switch C supports clock failure detection for system clock C supports auto clock switch once clock failure detected C supports exception (nmi) generated once a clock failure detected C supports divided clock out put ? gpio C four i/o modes C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level trigger setting C supports high driver and high sink curren t i / o (up to 20 ma at 5v) C supports software selectable slew rate control C supports up to 8 1 / 49 / 35 gpios for lqfp100/64/48 respectively ? timer /pwm C supports 4 sets of timer s /pwm timer mode pwm mode t m_cnt_out pwm_ch0 tm_ext pwm_ch1 (complementary) C timer mode ? supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle and continuous counting operation modes ? supports event counting function to count the eve nt from external pin ? supports input capture function to capture or reset counter value ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated ? support timer0 ~ timer3 time - out interrupt signal or capture interrupt signal to trigger pwm, eadc and pdma function ? supports inter - timer trigger mode C pwm mode ? supports maximum clock frequency up to 72 mhz ? supports independent mode for 4 sets of independent pwm output channel ? supports complementary mode for 4 sets of complementary pai red pwm output channel with 12 - bit dead - time generator ? supports 12 - bit pre - scalar from 1 to 4096
nuc126 aug . 08 , 201 8 page 12 of 140 rev 1 .0 4 nuc126 series datasheet ? supports 16 - bit resolution pwm counter, each timer provides 1 pwm counter ? supports up, down and up/down counter operation type ? supports one - shot or auto - reload counter operation mode ? supports mask function and tri - state enable for each pwm pin ? supports brake function ? supports interrupt when pwm counter match zero, period value or compared value, and brake condition happened ? supports trigger adc when pwm counter match zero, period value or compared value ? watchdog timer C supports m ultiple clock sources from lirc (default selection) , hclk/2048 and lxt C 8 selectable time - out period from 1.6ms ~ 26.0sec (depend ing on clock source) C able to wake up from power - down or idle mode C interrupt or reset selectable on watchdog time - out ? window watchdog timer C supports m ultiple clock sources from hclk/2048 (default selection) and lirc C w indow set by 6 - bit counter with 11 - bit prescale C interrupt or reset selectable on t ime - out ? rtc C supports separate battery power pin v bat C supports software compensation by setting frequency compensate register (fcr) C supports rtc counter (second, minute, hour) and calendar counter (day, month, year) C supports alarm registers (second, minute, hour, day, month, year) C supports alarm mask registers C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports wake - up function ? pwm C supports maximum clock freque n cy up to144 mhz C supports up to two pwm modules, each module provides 6 output channels. C supports independent mode for pwm output/capture input channel C supports complementary mode for 2 complementary paired pwm output channel ? de ad - time insertion with 12 - bit resolution ? two compared values during one period C supports 12 - bit pre - scal a r from 1 to 4096 C supports 16 - bit resolution pwm counter ? up, down and up/down counter operation type C supports mask function and tri - state enable for each pwm pin C supports brake function ? brake source from pin and system safety events : clock failed, brown - out detection and cpu lockup. ? noise filter for brake source from pin ? edge detect brake source to control brake state until brake interrupt cleared ? level detect brake source to auto recover function after brake condition removed C supports interrupt on the following events: ? pwm counter match zero, period value or compared value ? brake condition happened C supports trigger adc on the following events:
nuc126 aug . 08 , 201 8 page 13 of 140 rev 1 .0 4 nuc126 series datasheet ? pwm counter match zero, period value or compared value C support s up to 12 c apture input channels with 16 - bit resolution C supports r ising or falling capture condition C supports input rising/falling capture interrupt C supports rising/falling capture with counter reload opt ion ? usci C supports up to 3 sets of usci usci uart mode spi mode i 2 c m ode usci_clk - spi_clk scl usci_ctl0 ncts spi_ss - usci_ctl1 nrts - - usci_dat0 r x spi_mosi sda usci_dat1 tx spi_miso - C uart mode ? supports one transmit buffer and two receive buffer for data payload ? supports hardware auto flow control function ? supports programmable baud - rate generator ? support 9 - bit data transfer (support 9 - bit rs - 485) ? baud rate detection possible by built - in capture event of baud rate generator ? supports wake - up function (data and ncts wakeup only) C spi mode ? supports master or slave mode operation (the maximum frequency -- master = fpclk / 2, slave = fpclk / 5) ? supports one transmit buffer and two receive buffers for data payload ? configurable bit length of a transf er word from 4 to 16 - bit ? supports msb first or lsb first transfer sequence ? supports word suspend function ? supports 3 - wire, no slave select signal, bi - direction interface ? supports wake - up function by slave select signal in slave mode ? supports one data chann el half - duplex transfer C i 2 c mode ? full master and slave device capability ? supports of 7 - bit addressing, as well as 10 - bit addressing ? communication in standard mode (100 kbit/s) or in fast mode (up to 400 kbit/s) ? supports multi - master bus ? supports one transm it buffer and two receive buffer for data payload ? supports 10 - bit bus time - out capability ? supports bus monitor mode. ? supports power down wake - up by data toggle or address match ? supports setup/hold time programmable ? supports multiple address recognition (two slave address with mask option) ? uart C supports up to 3 sets of uart C full - duplex asynchronous communications C separates receive and transmit 16/16 bytes entry fifo for data payloads C supports hardware auto - flow control (rx, tx, cts and rts) C programmable r eceiver buffer trigger level C supports programmable baud rate generator for each channel individually C supports 8 - bit receiver buffer time - out detection function C programmable transmitting data delay time between the last stop and the next start bit by settin g dly (uart_tout [15:8])
nuc126 aug . 08 , 201 8 page 14 of 140 rev 1 .0 4 nuc126 series datasheet C supports auto - baud rate measurement and baud rate compensation function C supports break error, frame error, parity error and receive/transmit buffer overflow detection function C fully programmable serial - interface characteristics ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation C supports irda sir function mode ? supports for 3/ 16 bit duration for normal mode C supports lin function mode ? supports lin master/slave mode ? supports programmable break generation function for transmitter ? supports break detection function for receiver C supports rs - 485 mode ? supports rs - 485 9 - bit mode ? supports hardware or software enables to program nrts pin to control rs - 485 transmission direction C supports ncts, incoming data, received data fifo reached threshold and rs - 485 address match (aad mode) wake - up function C supports pdma transfer ? smart card hos t (sc) C supports up to two smart card host s sc mode uart mode sc_data rx sc_clk t x sc_cd - sc_pwr - sc_rst - C sc mode ? supports up to two iso - 7816 - 3 port s ? compliant to iso - 7816 - 3 t=0, t=1 ? separate receive / transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? one 24 - bit and two 8 - bit time - out counters for answer to request (atr) and waiting times processing ? supports auto inve rse convention function ? supports transmitter and receiver error retry and error limit function ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detecting the card is removal C uart mode ? full duplex, asynchronous communications ? supports receiving / transmitting 4 - bytes fifo ? supports programmable baud rate generator for each channel ? programmable even, odd or no parity b it generation and detection ? programmable stop bit, 1 or 2 stop bit generation ? spi /i 2 s
nuc126 aug . 08 , 201 8 page 15 of 140 rev 1 .0 4 nuc126 series datasheet C supports up to two spi/i2s controllers spi mode i 2 s mode spi_clk i2s_bclk spi_ss i2s_lrclk spi_mosi i2s_do spi_miso i2s_di - i2s_mclk C spi mode ? supports master or slave mode operation ? configurable bit length of a transfer word from 8 to 32 - bit ? provides separate 4 - /8 - level depth transmit and receive fifo buffers ? supports msb first or lsb first transfer sequence ? supports byte reorder function ? supports pdma transfer C i2s mode ? supports master or slave mode operation ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes in i2s mode ? provides separate 4 - level depth transmit and receive fifo buffers in i2s mode ? supports monaural and stereo audio data in i2s mode ? supports pcm mode a, pcm mode b, i2s and msb justified data format in i2s mode ? supports pdma transfer ? i 2 c C supports up to two sets of i2c device C supports master/slave mode C supports bidirectional data transfer between masters and slaves C supports multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C supports 14 - bit time - out counter requesting the i2c interrupt if the i2c bus hangs up and timer - out counter overflows C programmable clocks allow versatile rate control C supports multiple add ress recognition, four slave address with mask option C supports two - level buffer function C supports setup/hold time programmable C supports wake - up function ? usb 2.0 fs device controller C crystal - less usb 2.0 fs device C compliant to usb specification version 2.0 C on - chip usb transceiver C supports control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C supports usb 2.0 link power management (lpm) C provide s 8 programmable endpoints C supports 512 bytes internal sram as usb buffer C provide s remote wake - up capability C on - chip 5v to 3.3v ldo for usb phy
nuc126 aug . 08 , 201 8 page 16 of 140 rev 1 .0 4 nuc126 series datasheet ? adc C supports 12 - bit sar adc C 12 - bit resolution and 10 - bit accuracy is guaranteed C analog input voltage range: 0~ av dd C supports e xternal v ref pin C up to 20 single - end analog input channels C maximum adc peripheral clock frequency is 16 mhz C conversion rate up to 800k sps at 5v C configurable adc internal sampling time C supports single - scan, single - cycle - scan, and continuous scan and scan on enabled channels C supp orts individual conversion result register with valid and overrun indicators for each channel C supports digital comparator to monitor conversion result and user can select whether to generate an interrupt when conversion result matches the compare register setting C an a/d conversion can be triggered by: ? software enable ? external pin (stadc) ? timer 0~3 overflow pulse trigger ? pwm triggers with optional start delay period C supports 4 internal channels for ? operational amplifier output ? band - gap vbg input ? temperature sensor input ? vbat voltage measure C supports internal reference voltage: 2.048v, 2.560v, 3.072v and 4.096v C supports pdma transfer ? analog comparator C supports u p to 2 rail - to - rail analog comparator s C supports 4 multiplexed i/o pins at positive node. C supports i/o pin and internal voltage s at negative node C support selectable internal voltage reference from : ? band - gap v bg ? v oltage divider source from av dd and internal reference voltage. C supports programmable hysteresis C supports programmable speed and power consumption C interrupt s generated when compare result s change , interrupt event condition is programmable. C supports power - down wake - up C supports triggers for break events and cycle - by - cycle control for pwm ? cyclic redundancy calculation unit C supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 C programmable initial value C supports programmable order reverse setting for input data and crc checksum C supports programmable 1 s complement setting for input data and crc checksum. C supports 8/16/32 - b it of data width C interrupt generated once checksum error occurs ? user configurable vdd1= 1.8 ~5.5 v io i nterface C s upports uart0, spi0 and i2c0 ? supports 96 - bit unique id (uid) ? supports 128 - bit unique customer id (ucid) ? one built - in temperature sensor with 1 r esolution
nuc126 aug . 08 , 201 8 page 17 of 140 rev 1 .0 4 nuc126 series datasheet ? brown - out detector C with 8 levels: 4. 3 v/ 3. 7 v/ 2.7v/ 2.2v C supports brown - o ut interrupt and reset option ? low voltage reset C threshold voltage levels: 2 . 0 v ? power consumption C chip power down current < 10 ua with ram data retention. C vbat power domain operating current <1.5 ua ? operating temperature: - 40 ~ 105 ? packages C all green package (ro hs ) C lqfp 100 - pin C lqfp 64 - pin(7mmx7mm) C lqfp 48 - pin C qfn 48 - pin
nuc126 aug . 08 , 201 8 page 18 of 140 rev 1 .0 4 nuc126 series datasheet 3 abbreviations 3.1 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output h clk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sd secure digital spi serial peripheral interface
nuc126 aug . 08 , 201 8 page 19 of 140 rev 1 .0 4 nuc126 series datasheet sps samples per second tdes triple data encryption standard tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3.1 - 1 list of abbreviations
nuc126 aug . 08 , 201 8 page 20 of 140 rev 1 .0 4 nuc126 series datasheet 4 parts information li st and pin configura tion 4.1 numicro ? nuc126 selection guide 4.1.1 numicro ? nuc126 naming rule n u c 1 2 6 x x 4 x e a r m C c o r t e ? - m 0 p r o d u c t l i n e f u n c t i o n 2 x : u s b l i n e f l a s h r o m e : 1 2 8 k g : 2 5 6 k t e m p e r a t u r e v e r s i o n a : b : s r a m s i z e 4 : 2 0 k p a c k a g e t y p e l : l q f p 4 8 7 x 7 m m s : l q f p 6 4 7 x 7 m m v : l q f p 1 0 0 1 4 x 1 4 m m e : - 4 0 o c ~ + 1 0 5 o c n : q f n 4 8 7 x 7 m m
nuc126 aug . 08 , 201 8 page 21 of 140 rev 1 .0 4 nuc126 series datasheet 4.1.2 numicro ? nuc126 usb series (m452 compatible) selection guide part number flash (kb) sram (kb) data flash(kb) sprom(kb) isp rom (kb) i/o timer /pwm pwm connectivity adc(12 - bit) acmp pdma vbat( rtc ) v ddio ebi icp / i a p / i s p package usbd usci* uart sc/uart spi /i 2 s i 2 c nuc126 n e4ae 128 20 conf* 2 4 35 4 1 0 1 3 3 2 2 2 9 - ch 2 5 qfn 4 8 nuc126le4ae 128 20 conf* 2 4 35 4 1 0 1 3 3 2 2 2 9 - ch 2 5 lqfp 4 8 nuc126lg4ae 256 20 conf* 2 4 35 4 1 0 1 3 3 2 2 2 9 - ch 2 5 lqfp 48 nuc126 s e4ae 128 20 conf* 2 4 49 4 12 1 3 3 2 2 2 15 - ch 2 5 lqfp 64 * nuc126 s g4ae 256 20 conf* 2 4 49 4 12 1 3 3 2 2 2 15 - ch 2 5 lqfp 64 * nuc126vg4ae 256 20 conf* 2 4 81 4 12 1 3 3 2 2 2 20 - ch 2 5 lqfp 100 conf*: configurable usci*: support uart, spi or i 2 c lqfp64 *: 7x7 mm
nuc126 aug . 08 , 201 8 page 22 of 140 rev 1 .0 4 nuc126 series datasheet 4.2 pin configuration 4.2.1 numicro ? nuc126 usb series qfn 48 p in diagram c orresponding part number: nuc126 ne4 ae figure 4.2 - 1 numicro ? nuc126 usb series qf n 48 - pin diagram q f n 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 q f n 4 8 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p b . 5 p b . 6 p b . 7 n r e s e t p d . 0 a v s s p d . 1 p d . 2 p d . 3 v b a t p f . 0 p f . 1 p e . 0 p c . 4 p c . 3 p c . 2 p c . 1 p c . 0 l d o _ c a p v s s p f . 4 p f . 3 p d . 7 p f . 2 u s b _ v d d 3 3 _ c a p p f . 7 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 p e . 1 2 p e . 1 1 p e . 1 0 p e . 7 / i c e _ d a t p e . 6 / i c e _ c l k p a . 3 p a . 2 p a . 1 p a . 0 v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 v d d i o p o w e r d o m a i n v b a t p o w e r d o m a i n t o p t r a n s p a r e n t v i e w v s s
nuc126 aug . 08 , 201 8 page 23 of 140 rev 1 .0 4 nuc126 series datasheet 4.2.2 numicro ? nuc126 usb series lqfp 48 p in diagram c orresponding part number: nuc126 le 4 ae , nuc126 lg 4 ae figure 4.2 - 2 numicro ? nuc126 usb series lqfp 48 - pin diagram l q f p 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p b . 5 p b . 6 p b . 7 n r e s e t p d . 0 a v s s p d . 1 p d . 2 p d . 3 v b a t p f . 0 p f . 1 p e . 0 p c . 4 p c . 3 p c . 2 p c . 1 p c . 0 l d o _ c a p v s s p f . 4 p f . 3 p d . 7 p f . 2 u s b _ v d d 3 3 _ c a p p f . 7 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 p e . 1 2 p e . 1 1 p e . 1 0 p e . 7 / i c e _ d a t p e . 6 / i c e _ c l k p a . 3 p a . 2 p a . 1 p a . 0 v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 v d d i o p o w e r d o m a i n v b a t p o w e r d o m a i n
nuc126 aug . 08 , 201 8 page 24 of 140 rev 1 .0 4 nuc126 series datasheet 4.2.3 numicro ? nuc126 usb series lqfp 64 p in diagram c orresponding part number: nuc126 s e 4 ae , nuc126 s g 4 ae figure 4.2 - 3 numicro ? nuc126 usb series lqfp 64 - pin diagram l q f p 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 1 5 p b . 5 p b . 6 p b . 7 n r e s e t p d . 0 a v s s p d . 8 p d . 9 p d . 1 p d . 2 p d . 3 v b a t p f . 0 p f . 1 p f . 2 p c . 5 p c . 4 p c . 3 p c . 2 p c . 1 p c . 0 l d o _ c a p v d d v s s p f . 4 p f . 3 p d . 7 p d . 1 5 p d . 1 4 p d . 1 3 p d . 1 2 u s b _ v d d 3 3 _ c a p p f . 7 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 p e . 1 2 p e . 1 1 p e . 1 0 p e . 9 p e . 8 p e . 7 / i c e _ d a t p e . 6 / i c e _ c l k p c . 7 p c . 6 p a . 3 p a . 2 p a . 1 p a . 0 v s s v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 8 p b . 1 1 p e . 2 v d d i o p o w e r d o m a i n v b a t p o w e r d o m a i n
nuc126 aug . 08 , 201 8 page 25 of 140 rev 1 .0 4 nuc126 series datasheet 4.2.4 numicro ? nuc126 usb series lqfp 100 p in diagram c orresponding part number: nuc126 vg 4 ae figure 4.2 - 4 numicro ? nuc126 usb series lqfp 100 - pin diagram l q f p 1 0 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 p b . 1 3 p b . 1 4 p b . 1 5 p b . 5 p b . 6 p b . 7 n r e s e t p d . 0 a v s s v d d v s s p c . 8 p d . 8 p d . 9 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 p e . 3 p d . 6 v b a t p f . 0 p f . 1 p f . 2 p c . 5 p e . 0 p c . 4 p c . 3 p c . 2 p c . 1 p c . 0 p c . 1 4 p c . 1 3 p c . 1 2 p c . 1 1 p c . 1 0 p c . 9 l d o _ c a p v d d v s s p f . 4 p f . 3 p d . 7 p d . 1 5 p d . 1 4 p d . 1 3 p d . 1 2 p d . 1 1 p d . 1 0 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 p e . 1 2 p e . 1 1 p e . 1 0 p e . 9 p e . 8 p e . 1 v d d v s s p a . 4 p a . 5 p a . 6 p a . 7 p a . 9 p a . 8 p e . 7 / i c e _ d a t p e . 6 / i c e _ c l k p e . 5 p e . 4 p c . 7 p c . 6 p f . 7 u s b _ v d d 3 3 _ c a p p b . 1 2 p a . 3 p a . 2 p a . 1 p a . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 v s s v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 8 p b . 9 p b . 1 0 p b . 1 1 p e . 2 v d d i o p o w e r d o m a i n v b a t p o w e r d o m a i n
nuc126 aug . 08 , 201 8 page 26 of 140 rev 1 .0 4 nuc126 series datasheet 4.3 pin description 4.3.1 nuc126 usb series p in description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gp 0 _mfpl[3:0]=0x0. pa.9 mfp5 means sys_gp 0 _mfph[7:4]=0x5. 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description 1 pb.13 i/o mfp0 general purpose digital i/o pin. adc0_ch10 a mfp1 adc0 channel 10 analog input. 2 pb.14 i/o mfp0 general purpose digital i/o pin. adc0_ch11 a mfp1 adc0 channel 11 analog input. 1 3 pb.15 i/o mfp0 general purpose digital i/o pin. adc0_ch12 a mfp1 adc0 channel 12 analog input. acmp0_p3 a mfp5 analog comparator 0 positive input 3 pin. ebi_ncs1 o mfp7 ebi chip select 1 output pin. 1 2 4 pb.5 i/o mfp0 general purpose digital i/o pin. adc0_ch13 a mfp1 adc0 channel 13 analog input. spi0_mosi i/o mfp2 spi0 mosi (master out, slave in) pin. spi1_mosi i/o mfp3 spi1 mosi (master out, slave in) pin. acmp0_p2 a mfp5 analog comparator 0 positive input 2 pin. sc1_rst o mfp6 smart card 1 reset pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. uart2_rxd i mfp9 uart 2 data receiver input pin. 2 3 5 pb.6 i/o mfp0 general purpose digital i/o pin. adc0_ch14 a mfp1 adc0 channel 14 analog input. spi0_miso i/o mfp2 spi0 miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. acmp0_p1 a mfp5 analog comparator 0 positive input 1 pin. sc1_pwr o mfp6 smart card 1 power pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 3 4 6 pb.7 i/o mfp0 general purpose digital i/o pin. adc0_ch15 a mfp1 adc0 channel 15 analog input. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin. usci2_ctl1 i/o mfp4 usci2 control 1 pin.
nuc126 aug . 08 , 201 8 page 27 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description acmp0_p0 a mfp5 analog comparator 0 positive input 0 pin. sc1_dat i/o mfp6 smart card 1 data pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 4 5 7 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 5 6 8 pd.0 i/o mfp0 general purpose digital i/o pin. spi0_i2smclk i/o mfp1 spi0 i2s master clock output pin spi1_i2smclk i/o mfp2 spi1 i2s master clock output pin uart0_rxd i mfp3 uart0 data receiver input pin. usci2_ctl0 i/o mfp4 usci2 control 0 pin. acmp1_n a mfp5 analog comparator 1 negative input pin. sc1_clk o mfp6 smart card 1 clock pin. int3 i mfp8 external interrupt 3 input pin. 6 7 9 av ss p mfp0 ground pin for analog circuit. 10 v dd p mfp0 power supply for i/o ports and ldo source for internal pll and digital circuit. 11 v ss p mfp0 ground pin for digital circuit. 12 pc.8 i/o mfp0 general purpose digital i/o pin. adc0_ch16 a mfp1 adc0 channel 16 analog input. uart0_nrts o mfp3 uart0 request to send output pin. 8 13 pd.8 i/o mfp0 general purpose digital i/o pin. adc0_ch17 a mfp1 adc0 channel 17 analog input. uart0_ncts i mfp3 uart0 clear to send input pin. usci2_ctl1 i/o mfp4 usci2 control 1 pin. tm2 i/o mfp6 timer2 event counter input/toggle output pin. ebi_ncs0 o mfp7 ebi chip select 0 output pin. 9 14 pd.9 i/o mfp0 general purpose digital i/o pin. adc0_ch18 a mfp1 adc0 channel 18 analog input. uart0_rxd i mfp3 uart0 data receiver input pin. usci2_ctl0 i/o mfp4 usci2 control 0 pin. acmp1_p3 a mfp5 analog comparator 1 positive input 3 pin. tm3 i/o mfp6 timer3 event counter input/toggle output pin. ebi_ale o mfp7 ebi address latch enable output pin. 7 10 15 pd.1 i/o mfp0 general purpose digital i/o pin. adc0_ch19 a mfp1 adc0 channel 19 analog input.
nuc126 aug . 08 , 201 8 page 28 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description pwm0_sync_in i mfp2 pwm0 counter synchronous trigger input pin. uart0_txd o mfp3 uart0 data transmitter output pin. usci2_clk i/o mfp4 usci2 clock pin. acmp1_p2 a mfp5 analog comparator 1 positive input 2 pin. tm0 i/o mfp6 timer0 event counter input/toggle output pin. ebi_nrd o mfp7 ebi read enable output pin. 8 11 16 pd.2 i/o mfp0 general purpose digital i/o pin. adc0_st i mfp1 adc0 external trigger input pin. tm0_ext i/o mfp3 timer0 external capture input/toggle output pin. usci2_dat0 i/o mfp4 usci2 data 0 pin. acmp1_p1 a mfp5 analog comparator 1 positive input 1 pin. pwm0_brake0 i mfp6 pwm0 brake 0 input pin. ebi_nwr o mfp7 ebi write enable output pin. int0 i mfp8 external interrupt 0 input pin. 9 12 17 pd.3 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp1 timer2 event counter input/toggle output pin. spi0_i2smclk i/o mfp2 spi0 i2s master clock output pin tm1_ext i/o mfp3 timer1 external capture input/toggle output pin. usci2_dat1 i/o mfp4 usci2 data 1 pin. acmp1_p0 a mfp5 analog comparator 1 positive input 0 pin. pwm0_brake1 i mfp6 pwm0 brake 1 input pin. ebi_mclk o mfp7 ebi external clock output pin. int1 i mfp8 external interrupt 1 input pin. 18 pd.4 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp2 spi1 serial clock pin. i2c0_sda i/o mfp3 i2c0 data input/output pin. uart2_nrts o mfp4 uart2 request to send output pin. pwm0_brake0 i mfp5 pwm0 brake 0 input pin. tm0 i/o mfp6 timer0 event counter input/toggle output pin. 19 pd.5 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out spi1_miso i/o mfp2 spi1 miso (master in, slave out) pin. i2c0_scl i/o mfp3 i2c0 clock pin. uart2_ncts i mfp4 uart2 clear to send input pin.
nuc126 aug . 08 , 201 8 page 29 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description pwm0_brake1 i mfp5 pwm0 brake 1 input pin. tm1 i/o mfp6 timer1 event counter input/toggle output pin. 20 pe.3 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp2 spi1 mosi (master out, slave in) pin. uart2_rxd i mfp4 uart2 data receiver input pin. pwm0_ch3 i/o mfp6 pwm0 channel 3 output/capture input. 21 pd.6 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out spi1_ss i/o mfp2 spi1 slave select pin. uart0_rxd i mfp3 uart0 data receiver input pin. uart2_txd o mfp4 uart2 data transmitter output pin. acmp0_o o mfp5 analog comparator 0 output pin. pwm0_ch5 i/o mfp6 pwm0 channel 5 output/capture input. ebi_nwr o mfp7 ebi write enable output pin. 10 13 22 v bat p mfp0 power supply by batteries for rtc. 11 14 23 pf.0 i/o mfp0 general purpose digital i/o pin. x32_out o mfp1 external 32.768 khz crystal output pin. usci2_ctl1 i/o mfp5 usci2 control 1 pin. int5 i mfp8 external interrupt 5 input pin. 12 15 24 pf.1 i/o mfp0 general purpose digital i/o pin. x32_in i mfp1 external 32.768 khz crystal input pin. usci2_ctl0 i/o mfp5 usci2 control 0 pin. pwm1_brake0 i mfp6 pwm1 brake 0 input pin. 13 16 25 pf.2 i/o mfp0 general purpose digital i/o pin. usci2_clk i/o mfp5 usci2 clock pin. pwm1_brake1 i mfp6 pwm1 brake 1 input pin. 26 pd.10 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp4 timer2 event counter input/toggle output pin. usci2_dat0 i/o mfp5 usci2 data 0 pin. 27 pd.11 i/o mfp0 general purpose digital i/o pin. tm3 i/o mfp4 timer3 event counter input/toggle output pin. usci2_dat1 i/o mfp5 usci2 data 1 pin. 17 28 pd.12 i/o mfp0 general purpose digital i/o pin. usci1_ctl0 i/o mfp1 usci1 control 0 pin.
nuc126 aug . 08 , 201 8 page 30 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description spi1_ss i/o mfp2 spi1 slave select pin. uart0_txd o mfp3 uart0 data transmitter output pin. pwm1_ch0 i/o mfp6 pwm1 channel 0 output/capture input. ebi_adr16 o mfp7 ebi address bus bit 16. 18 29 pd.13 i/o mfp0 general purpose digital i/o pin. usci1_dat1 i/o mfp1 usci1 data 1 pin. spi1_mosi i/o mfp2 spi1 mosi (master out, slave in) pin. uart0_rxd i mfp3 uart0 data receiver input pin. pwm1_ch1 i/o mfp6 pwm1 channel 1 output/capture input. ebi_adr17 o mfp7 ebi address bus bit 17. 19 30 pd.14 i/o mfp0 general purpose digital i/o pin. usci1_dat0 i/o mfp1 usci1 data 0 pin. spi1_miso i/o mfp2 spi1 miso (master in, slave out) pin. uart0_ncts i mfp3 uart0 clear to send input pin. pwm1_ch2 i/o mfp6 pwm1 channel 2 output/capture input. ebi_adr18 o mfp7 ebi address bus bit 18. 20 31 pd.15 i/o mfp0 general purpose digital i/o pin. usci1_clk i/o mfp1 usci1 clock pin. spi1_clk i/o mfp2 spi1 serial clock pin. uart0_nrts o mfp3 uart0 request to send output pin. pwm1_ch3 i/o mfp6 pwm1 channel 3 output/capture input. ebi_adr19 o mfp7 ebi address bus bit 19. 14 21 32 pd.7 i/o mfp0 general purpose digital i/o pin. usci1_ctl1 i/o mfp1 usci1 control 1 pin. spi0_i2smclk i/o mfp2 spi0 i2s master clock output pin pwm0_sync_in i mfp3 pwm0 counter synchronous trigger input pin. tm1 i/o mfp4 timer1 event counter input/toggle output pin. acmp0_o o mfp5 analog comparator 0 output pin. pwm0_ch5 i/o mfp6 pwm0 channel 5 output/capture input. ebi_nrd o mfp7 ebi read enable output pin. 15 22 33 pf.3 i/o mfp0 general purpose digital i/o pin. xt1_out o mfp1 external 4~24 mhz (high speed) crystal output pin. i2c1_scl i/o mfp3 i2c1 clock pin. 16 23 34 pf.4 i/o mfp0 general purpose digital i/o pin.
nuc126 aug . 08 , 201 8 page 31 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description xt1_in i mfp1 external 4~24 mhz (high speed) crystal input pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. 17 24 35 v ss p mfp0 ground pin for digital circuit. 25 36 v dd p mfp0 power supply for i/o ports and ldo source for internal pll and digital circuit. 18 26 37 ldo_cap a mfp0 ldo output pin. 38 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_i2smclk i/o mfp2 spi0 i2s master clock output pin i2c1_scl i/o mfp3 i2c1 clock pin. usci2_ctl1 i/o mfp4 usci2 control 1 pin. pwm1_ch0 i/o mfp6 pwm1 channel 0 output/capture input. 39 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp2 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. usci2_dat1 i/o mfp4 usci2 data 1 pin. pwm1_ch1 i/o mfp6 pwm1 channel 1 output/capture input. 40 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp2 spi0 miso (master in, slave out) pin. usci2_clk i/o mfp4 usci2 clock pin. pwm1_ch2 i/o mfp6 pwm1 channel 2 output/capture input. 41 pc.12 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp2 spi0 serial clock pin. usci2_ctl0 i/o mfp4 usci2 control 0 pin. pwm1_ch3 i/o mfp6 pwm1 channel 3 output/capture input. 42 pc.13 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp2 spi0 slave select pin. usci2_dat0 i/o mfp4 usci2 data 0 pin. pwm1_ch4 i/o mfp6 pwm1 channel 4 output/capture input. 43 pc.14 i/o mfp0 general purpose digital i/o pin. pwm1_ch5 i/o mfp6 pwm1 channel 5 output/capture input. 19 27 44 pc.0 i/o mfp0 general purpose digital i/o pin. sc0_dat i/o mfp1 smart card 0 data pin. spi0_clk i/o mfp2 spi0 serial clock pin. uart2_ncts i mfp3 uart2 clear to send input pin.
nuc126 aug . 08 , 201 8 page 32 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description usci0_dat0 i/o mfp4 usci0 data 0 pin. acmp0_wlat i mfp5 analog comparator 0 window latch input pin pwm0_ch0 i/o mfp6 pwm0 channel 0 output/capture input. ebi_ad8 i/o mfp7 ebi address/data bus bit 8. int2 i mfp8 external interrupt 2 input pin. 20 28 45 pc.1 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out sc0_clk o mfp2 smart card 0 clock pin. uart2_nrts o mfp3 uart2 request to send output pin. usci0_dat1 i/o mfp4 usci0 data 1 pin. acmp1_wlat i mfp5 analog comparator 1 window latch input pin pwm0_ch1 i/o mfp6 pwm0 channel 1 output/capture input. ebi_ad9 i/o mfp7 ebi address/data bus bit 9. 21 29 46 pc.2 i/o mfp0 general purpose digital i/o pin. sc0_rst o mfp1 smart card 0 reset pin. spi0_ss i/o mfp2 spi0 slave select pin. uart2_txd o mfp3 uart2 data transmitter output pin. usci0_ctl1 i/o mfp4 usci0 control 1 pin. acmp1_o o mfp5 analog comparator 1 output pin. pwm0_ch2 i/o mfp6 pwm0 channel 2 output/capture input. ebi_ad10 i/o mfp7 ebi address/data bus bit 10. 22 30 47 pc.3 i/o mfp0 general purpose digital i/o pin. sc0_pwr o mfp1 smart card 0 power pin. spi0_mosi i/o mfp2 spi0 mosi (master out, slave in) pin. uart2_rxd i mfp3 uart2 data receiver input pin. usci0_ctl0 i/o mfp5 usci0 control 0 pin. pwm0_ch3 i/o mfp6 pwm0 channel 3 output/capture input. ebi_ad11 i/o mfp7 ebi address/data bus bit 11. 23 31 48 pc.4 i/o mfp0 general purpose digital i/o pin. sc0_ncd i mfp1 smart card 0 card detect pin. spi0_miso i/o mfp2 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i2c1 clock pin. usci0_clk i/o mfp5 usci0 clock pin. pwm0_ch4 i/o mfp6 pwm0 channel 4 output/capture input.
nuc126 aug . 08 , 201 8 page 33 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description ebi_ad12 i/o mfp7 ebi address/data bus bit 12. 24 49 pe.0 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp2 spi0 serial clock pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. tm2_ext i/o mfp4 timer2 external capture input/toggle output pin. sc0_ncd i mfp5 smart card 0 card detect pin. pwm0_ch0 i/o mfp6 pwm0 channel 0 output/capture input. ebi_ncs1 o mfp7 ebi chip select 1 output pin. int4 i mfp8 external interrupt 4 input pin. 32 50 pc.5 i/o mfp0 general purpose digital i/o pin. spi0_i2smclk i/o mfp2 spi0 i2s master clock output pin i2c1_sda i/o mfp3 i2c1 data input/output pin. usci0_dat0 i/o mfp4 usci0 data 0 pin. pwm0_ch5 i/o mfp6 pwm0 channel 5 output/capture input. ebi_ad13 i/o mfp7 ebi address/data bus bit 13. 33 51 pc.6 i/o mfp0 general purpose digital i/o pin. usci0_dat1 i/o mfp4 usci0 data 1 pin. acmp1_o o mfp5 analog comparator 1 output pin. pwm1_ch0 i/o mfp6 pwm1 channel 0 output/capture input. ebi_ad14 i/o mfp7 ebi address/data bus bit 14. 34 52 pc.7 i/o mfp0 general purpose digital i/o pin. usci0_ctl1 i/o mfp4 usci0 control 1 pin. pwm1_ch1 i/o mfp6 pwm1 channel 1 output/capture input. ebi_ad15 i/o mfp7 ebi address/data bus bit 15. 53 pe.4 i/o mfp0 general purpose digital i/o pin. i2c0_scl i/o mfp2 i2c0 clock pin. i2c1_scl i/o mfp3 i2c1 clock pin. usci0_ctl0 i/o mfp4 usci0 control 0 pin. sc0_pwr o mfp5 smart card 0 power pin. pwm1_brake0 i mfp6 pwm1 brake 0 input pin. ebi_ncs0 o mfp7 ebi chip select 0 output pin. int0 i mfp8 external interrupt 0 input pin. 54 pe.5 i/o mfp0 general purpose digital i/o pin. i2c0_sda i/o mfp2 i2c0 data input/output pin.
nuc126 aug . 08 , 201 8 page 34 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description i2c1_sda i/o mfp3 i2c1 data input/output pin. usci0_clk i/o mfp4 usci0 clock pin. sc0_rst o mfp5 smart card 0 reset pin. pwm1_brake1 i mfp6 pwm1 brake 1 input pin. ebi_ale o mfp7 ebi address latch enable output pin. int1 i mfp8 external interrupt 1 input pin. 25 35 55 pe.6 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin. i2c0_scl i/o mfp2 i2c0 clock pin. uart0_rxd i mfp3 uart0 data receiver input pin. 26 36 56 pe.7 i/o mfp0 general purpose digital i/o pin. ice_dat o mfp1 serial wired debugger data pin. i2c0_sda i/o mfp2 i2c0 data input/output pin. uart0_txd o mfp3 uart0 data transmitter output pin. 57 pa.8 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out i2c1_scl i/o mfp2 i2c1 clock pin. uart1_txd o mfp3 uart1 data transmitter output pin. sc0_pwr o mfp4 smart card 0 power pin. sc1_rst o mfp5 smart card 1 reset pin. tm_brake0 i mfp6 timer brake 0 input pin. pwm0_brake0 i mfp7 pwm0 brake 0 input pin. tm1 i/o mfp8 timer1 event counter input/toggle output pin. 58 pa.9 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk i/o mfp1 spi1 i2s master clock output pin i2c1_sda i/o mfp2 i2c1 data input/output pin. uart1_rxd i mfp3 uart1 data receiver input pin. sc0_rst o mfp4 smart card 0 reset pin. sc1_pwr o mfp5 smart card 1 power pin. tm_brake1 i mfp6 timer brake 1 input pin. pwm1_brake1 i mfp7 pwm1 brake 1 input pin. tm2 i/o mfp8 timer2 event counter input/toggle output pin. 59 pa.7 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp2 spi1 serial clock pin.
nuc126 aug . 08 , 201 8 page 35 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description tm0_ext i/o mfp3 timer0 external capture input/toggle output pin. tm_brake1 i mfp6 timer brake 1 input pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7. 60 pa.6 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp2 spi1 miso (master in, slave out) pin. tm1_ext i/o mfp3 timer1 external capture input/toggle output pin. tm_brake2 i mfp6 timer brake 2 input pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. 61 pa.5 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp2 spi1 mosi (master out, slave in) pin. tm2_ext i/o mfp3 timer2 external capture input/toggle output pin. tm_brake3 i mfp6 timer brake 3 input pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 62 pa.4 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp2 spi1 slave select pin. tm3_ext i/o mfp3 timer3 external capture input/toggle output pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 63 v ss p mfp0 ground pin for digital circuit. 64 v dd p mfp0 power supply for i/o ports and ldo source for internal pll and digital circuit. 65 pe.1 i/o mfp0 general purpose digital i/o pin. tm3_ext i/o mfp3 timer3 external capture input/toggle output pin. sc0_ncd i mfp5 smart card 0 card detect pin. pwm0_ch1 i/o mfp6 pwm0 channel 1 output/capture input. 37 66 pe.8 i/o mfp0 general purpose digital i/o pin. uart1_txd o mfp1 uart1 data transmitter output pin. tm0 i/o mfp3 timer0 event counter input/toggle output pin. i2c1_scl i/o mfp4 i2c1 clock pin. sc0_pwr o mfp5 smart card 0 power pin. 38 67 pe.9 i/o mfp0 general purpose digital i/o pin. uart1_rxd i mfp1 uart1 data receiver input pin. tm1 i/o mfp3 timer1 event counter input/toggle output pin. i2c1_sda i/o mfp4 i2c1 data input/output pin. sc0_rst o mfp5 smart card 0 reset pin.
nuc126 aug . 08 , 201 8 page 36 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description 27 39 68 pe.10 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp1 spi1 miso (master in, slave out) pin. spi0_miso i/o mfp2 spi0 miso (master in, slave out) pin. uart1_ncts i mfp3 uart1 clear to send input pin. sc0_dat i/o mfp5 smart card 0 data pin. spi1_clk i/o mfp6 spi1 serial clock pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7. tm0_ext i/o mfp8 timer0 external capture input/toggle output pin. 28 40 69 pe.11 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp1 spi1 mosi (master out, slave in) pin. spi0_mosi i/o mfp2 spi0 mosi (master out, slave in) pin. uart1_nrts o mfp3 uart1 request to send output pin. sc0_clk o mfp5 smart card 0 clock pin. spi1_miso i/o mfp6 spi1 miso (master in, slave out) pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. tm1_ext i/o mfp8 timer1 external capture input/toggle output pin. 29 41 70 pe.12 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp1 spi1 slave select pin. spi0_ss i/o mfp2 spi0 slave select pin. uart1_txd o mfp3 uart1 data transmitter output pin. i2c0_scl i/o mfp4 i2c0 clock pin. spi1_mosi i/o mfp6 spi1 mosi (master out, slave in) pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. tm2_ext i/o mfp8 timer2 external capture input/toggle output pin. 30 42 71 pe.13 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp1 spi1 serial clock pin. spi0_clk i/o mfp2 spi0 serial clock pin. uart1_rxd i mfp3 uart1 data receiver input pin. i2c0_sda i/o mfp4 i2c0 data input/output pin. spi1_ss i/o mfp6 spi1 slave select pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. tm3_ext i/o mfp8 timer3 external capture input/toggle output pin. 31 43 72 v ddio p mfp0 power supply for pe.1, pe.8~pe.13. 32 44 73 usb_vbus p mfp0 power supply from usb host or hub.
nuc126 aug . 08 , 201 8 page 37 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description 33 45 74 usb_d - a mfp0 usb differential signal d+. 34 46 75 usb_d+ a mfp0 usb differential signal d - . 35 47 76 pf.7 i/o mfp0 general purpose digital i/o pin. 36 48 77 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 78 pb.12 i/o mfp0 general purpose digital i/o pin. pwm1_ch1 i/o mfp6 pwm1 channel 1 output/capture input. 37 49 79 pa.3 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp2 uart0 data receiver input pin. uart0_nrts o mfp3 uart0 request to send output pin. i2c0_scl i/o mfp4 i2c0 clock pin. sc0_pwr o mfp5 smart card 0 power pin. pwm1_ch2 i/o mfp6 pwm1 channel 2 output/capture input. ebi_ad3 i/o mfp7 ebi address/data bus bit 3. usci1_clk i/o mfp8 usci1 clock pin. 38 50 80 pa.2 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp2 uart0 data transmitter output pin. uart0_ncts i mfp3 uart0 clear to send input pin. i2c0_sda i/o mfp4 i2c0 data input/output pin. sc0_rst o mfp5 smart card 0 reset pin. pwm1_ch3 i/o mfp6 pwm1 channel 3 output/capture input. ebi_ad2 i/o mfp7 ebi address/data bus bit 2. usci1_ctl0 i/o mfp8 usci1 control 0 pin. 39 51 81 pa.1 i/o mfp0 general purpose digital i/o pin. uart1_nrts o mfp1 uart1 request to send output pin. uart1_rxd i mfp3 uart1 data receiver input pin. usci1_ctl1 i/o mfp4 usci1 control 1 pin. sc0_dat i/o mfp5 smart card 0 data pin. pwm1_ch4 i/o mfp6 pwm1 channel 4 output/capture input. ebi_ad1 i/o mfp7 ebi address/data bus bit 1. 40 52 82 pa.0 i/o mfp0 general purpose digital i/o pin. uart1_ncts i mfp1 uart1 clear to send input pin. uart1_txd o mfp3 uart1 data transmitter output pin. usci1_ctl0 i/o mfp4 usci1 control 0 pin. sc0_clk o mfp5 smart card 0 clock pin.
nuc126 aug . 08 , 201 8 page 38 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description pwm1_ch5 i/o mfp6 pwm1 channel 5 output/capture input. ebi_ad0 i/o mfp7 ebi address/data bus bit 0. int0 i mfp8 external interrupt 0 input pin. 83 pa.12 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk i/o mfp2 spi1 i2s master clock output pin uart2_rxd i mfp3 uart2 data receiver input pin. uart1_rxd i mfp4 uart1 data receiver input pin. tm_brake2 i mfp6 timer brake 2 input pin. 84 pa.13 i/o mfp0 general purpose digital i/o pin. uart2_txd o mfp3 uart2 data transmitter output pin. uart1_txd o mfp4 uart1 data transmitter output pin. tm_brake3 i mfp6 timer brake 3 input pin. 85 pa.14 i/o mfp0 general purpose digital i/o pin. uart2_ncts i mfp3 uart2 clear to send input pin. usci1_ctl1 i/o mfp4 usci1 control 1 pin. tm2 i/o mfp6 timer2 event counter input/toggle output pin. 86 pa.15 i/o mfp0 general purpose digital i/o pin. uart2_nrts o mfp3 uart2 request to send output pin. usci1_clk i/o mfp4 usci1 clock pin. tm3 i/o mfp6 timer3 event counter input/toggle output pin. 53 87 v ss p mfp0 ground pin for digital circuit. 41 54 88 v dd p mfp0 power supply for i/o ports and ldo source for internal pll and digital circuit. 42 55 89 av dd p mfp0 power supply for internal analog circuit. 43 56 90 v ref a mfp0 adc reference voltage input. note: this pin needs to be connected with a 1uf capacitor. 44 57 91 pb.0 i/o mfp0 general purpose digital i/o pin. adc0_ch0 a mfp1 adc0 channel 0 analog input. vdet_p0 a mfp2 voltage detector positive input 0 pin. uart2_rxd i mfp3 uart2 data receiver input pin. tm2 i/o mfp4 timer2 event counter input/toggle output pin. usci1_dat0 i/o mfp6 usci1 data 0 pin. ebi_nwrl o mfp7 ebi low byte write enable output pin. int1 i mfp8 external interrupt 1 input pin. tm1_ext i/o mfp10 timer1 external capture input/toggle output pin.
nuc126 aug . 08 , 201 8 page 39 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description 45 58 92 pb.1 i/o mfp0 general purpose digital i/o pin. adc0_ch1 a mfp1 adc0 channel 1 analog input. vdet_p1 a mfp2 voltage detector positive input 1 pin. uart2_txd o mfp3 uart2 data transmitter output pin. tm3 i/o mfp4 timer3 event counter input/toggle output pin. sc0_rst o mfp5 smart card 0 reset pin. pwm0_sync_out o mfp6 pwm0 counter synchronous trigger output pin. ebi_nwrh o mfp7 ebi high byte write enable output pin usci1_dat1 i/o mfp8 usci1 data 1 pin. 46 59 93 pb.2 i/o mfp0 general purpose digital i/o pin. adc0_ch2 a mfp1 adc0 channel 2 analog input. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin. uart1_rxd i mfp4 uart1 data receiver input pin. sc0_ncd i mfp5 smart card 0 card detect pin. tm_brake0 i mfp6 timer brake 0 input pin. ebi_ncs0 o mfp7 ebi chip select 0 output pin. usci0_dat0 i/o mfp8 usci0 data 0 pin. tm2_ext i/o mfp10 timer 2 external capture input/toggle output pin. 47 60 94 pb.3 i/o mfp0 general purpose digital i/o pin. adc0_ch3 a mfp1 adc0 channel 3 analog input. spi0_miso i/o mfp2 spi0 miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. uart1_txd o mfp4 uart1 data transmitter output pin. tm_brake1 i mfp6 timer brake 1 input pin. ebi_ale o mfp7 ebi address latch enable output pin. usci0_dat1 i/o mfp8 usci0 data 1 pin. tm 0 _ext i/o mfp10 timer 0 external capture input/toggle output pin. 48 61 95 pb.4 i/o mfp0 general purpose digital i/o pin. adc0_ch4 a mfp1 adc0 channel 4 analog input. spi0_ss i/o mfp2 spi0 slave select pin. spi1_ss i/o mfp3 spi1 slave select pin. uart1_ncts i mfp4 uart1 clear to send input pin. acmp0_n a mfp5 analog comparator 0 negative input pin.
nuc126 aug . 08 , 201 8 page 40 of 140 rev 1 .0 4 nuc126 series datasheet 4 8 pin 6 4 pin 1 00 pin pin name type mfp * description sc1_ncd i mfp6 smart card 1 card detect pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7. usci0_ctl1 i/o mfp8 usci0 control 1 pin. uart2_rxd i mfp 9 uart2 data receiver input pin. tm 1 _ext i/o mfp10 timer 1 external capture input/toggle output pin. 62 96 pb.8 i/o mfp0 general purpose digital i/o pin. adc0_ch5 a mfp1 adc0 channel 5 analog input. uart1_nrts o mfp4 uart1 request to send output pin. tm_brake2 i mfp5 timer brake 2 input pin. pwm0_ch2 i/o mfp6 pwm0 channel 2 output/capture input. usci0_ctl0 i/o mfp8 usci0 control 0 pin. 97 pb.9 i/o mfp0 general purpose digital i/o pin. adc0_ch6 a mfp1 adc0 channel 6 analog input. usci0_clk i/o mfp8 usci0 clock pin. 98 pb.10 i/o mfp0 general purpose digital i/o pin. adc0_ch7 a mfp1 adc0 channel 7 analog input. 63 99 pb.11 i/o mfp0 general purpose digital i/o pin. adc0_ch8 a mfp1 adc0 channel 8 analog input. 64 100 pe.2 i/o mfp0 general purpose digital i/o pin. adc0_ch9 a mfp1 adc0 channel 9 analog input. uart1_nrts o mfp4 uart1 request to send output pin. tm_brake3 i mfp5 timer brake 3 input pin. pwm0_ch2 i/o mfp6 pwm0 channel 2 output/capture input. usci0_ctl0 i/o mfp8 usci0 control 0 pin.
nuc126 aug . 08 , 201 8 page 41 of 140 rev 1 .0 4 nuc126 series datasheet 4.3.2 gpio multi - function pin summary mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gp 0 _mfpl[3:0]=0x0. pa.9 mfp5 means sys_gp 0 _mfph[7:4]=0x5. group pin name gpio mfp * type description acmp0 acmp0_n pb.4 mfp5 a analog comparator 0 negative input pin. acmp0_o pd.6 mfp5 o analog comparator 0 output pin. pd.7 mfp5 o acmp0_p0 pb.7 mfp5 a analog comparator 0 positive input 0 pin. acmp0_p1 pb.6 mfp5 a analog comparator 0 positive input 1 pin. acmp0_p2 pb.5 mfp5 a analog comparator 0 positive input 2 pin. acmp0_p3 pb.15 mfp5 a analog comparator 0 positive input 3 pin. acmp0_wlat pc.0 mfp5 i analog comparator 0 window latch input pin acmp1 acmp1_n pd.0 mfp5 a analog comparator 1 negative input pin. acmp1_o pc.2 mfp5 o analog comparator 1 output pin. pc.6 mfp5 o acmp1_p0 pd.3 mfp5 a analog comparator 1 positive input 0 pin. acmp1_p1 pd.2 mfp5 a analog comparator 1 positive input 1 pin. acmp1_p2 pd.1 mfp5 a analog comparator 1 positive input 2 pin. acmp1_p3 pd.9 mfp5 a analog comparator 1 positive input 3 pin. acmp1_wlat pc.1 mfp5 i analog comparator 1 window latch input pin adc0 adc0_ch0 pb.0 mfp1 a adc0 channel 0 analog input. adc0_ch1 pb.1 mfp1 a adc0 channel 1 analog input. adc0_ch2 pb.2 mfp1 a adc0 channel 2 analog input. adc0_ch3 pb.3 mfp1 a adc0 channel 3 analog input. adc0_ch4 pb.4 mfp1 a adc0 channel 4 analog input. adc0_ch5 pb.8 mfp1 a adc0 channel 5 analog input. adc0_ch6 pb.9 mfp1 a adc0 channel 6 analog input. adc0_ch7 pb.10 mfp1 a adc0 channel 7 analog input. adc0_ch8 pb.11 mfp1 a adc0 channel 8 analog input. adc0_ch9 pe.2 mfp1 a adc0 channel 9 analog input. adc0_ch10 pb.13 mfp1 a adc0 channel 10 analog input. adc0_ch11 pb.14 mfp1 a adc0 channel 11 analog input. adc0_ch12 pb.15 mfp1 a adc0 channel 12 analog input. adc0_ch13 pb.5 mfp1 a adc0 channel 13 analog input. adc0_ch14 pb.6 mfp1 a adc0 channel 14 analog input.
nuc126 aug . 08 , 201 8 page 42 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description adc0_ch15 pb.7 mfp1 a adc0 channel 15 analog input. adc0_ch16 pc.8 mfp1 a adc0 channel 16 analog input. adc0_ch17 pd.8 mfp1 a adc0 channel 17 analog input. adc0_ch18 pd.9 mfp1 a adc0 channel 18 analog input. adc0_ch19 pd.1 mfp1 a adc0 channel 19 analog input. adc0_st pd.2 mfp1 i adc0 external trigger input pin. clko clko pd.5 mfp1 o clock out pd.6 mfp1 o p a.8 mfp1 o pc.1 mfp1 o ebi ebi_ad0 pa.0 mfp7 i/o ebi address/data bus bit 0. ebi_ad1 pa.1 mfp7 i/o ebi address/data bus bit 1. ebi_ad2 pa.2 mfp7 i/o ebi address/data bus bit 2. ebi_ad3 pa.3 mfp7 i/o ebi address/data bus bit 3. ebi_ad4 pb.7 mfp7 i/o ebi address/data bus bit 4. pa.4 mfp7 i/o pe.13 mfp7 i/o ebi_ad5 pb.6 mfp7 i/o ebi address/data bus bit 5. pa.5 mfp7 i/o pe.12 mfp7 i/o ebi_ad6 pb.5 mfp7 i/o ebi address/data bus bit 6. pa.6 mfp7 i/o pe.11 mfp7 i/o ebi_ad7 pa.7 mfp7 i/o ebi address/data bus bit 7. pe.10 mfp7 i/o pb.4 mfp7 i/o ebi_ad8 pc.0 mfp7 i/o ebi address/data bus bit 8. ebi_ad9 pc.1 mfp7 i/o ebi address/data bus bit 9. ebi_ad10 pc.2 mfp7 i/o ebi address/data bus bit 10. ebi_ad11 pc.3 mfp7 i/o ebi address/data bus bit 11. ebi_ad12 pc.4 mfp7 i/o ebi address/data bus bit 12. ebi_ad13 pc.5 mfp7 i/o ebi address/data bus bit 13. ebi_ad14 pc.6 mfp7 i/o ebi address/data bus bit 14. ebi_ad15 pc.7 mfp7 i/o ebi address/data bus bit 15.
nuc126 aug . 08 , 201 8 page 43 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description ebi_adr16 pd.12 mfp7 o ebi address bus bit 16. ebi_adr17 pd.13 mfp7 o ebi address bus bit 17. ebi_adr18 pd.14 mfp7 o ebi address bus bit 18. ebi_adr19 pd.15 mfp7 o ebi address bus bit 19. ebi_ale pd.9 mfp7 o ebi address latch enable output pin. pe.5 mfp7 o pb.3 mfp7 o ebi_mclk pd.3 mfp7 o ebi external clock output pin. ebi_ncs0 pd.8 mfp7 o ebi chip select 0 output pin. pe.4 mfp7 o pb.2 mfp7 o ebi_ncs1 pb.15 mfp7 o ebi chip select 1 output pin. pe.0 mfp7 o ebi_nrd pd.1 mfp7 o ebi read enable output pin. pd.7 mfp7 o ebi_nwr pd.2 mfp7 o ebi write enable output pin. pd.6 mfp7 o ebi_nwrh pb.1 mfp7 o ebi high byte write enable output pin ebi_nwrl pb.0 mfp7 o ebi low byte write enable output pin. i2c0 i2c0_scl pd.5 mfp3 i/o i2c0 clock pin. pe.4 mfp2 i/o pe.6 mfp2 i/o pe.12 mfp4 i/o pa.3 mfp4 i/o i2c0_sda pd.4 mfp3 i/o i2c0 data input/output pin. pe.5 mfp2 i/o pe.7 mfp2 i/o pe.13 mfp4 i/o pa.2 mfp4 i/o i2c1 i2c1_scl pf.3 mfp3 i/o i2c1 clock pin. pc.9 mfp3 i/o pc.4 mfp3 i/o pe.4 mfp3 i/o p a.8 mfp 2 i/o
nuc126 aug . 08 , 201 8 page 44 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pe.8 mfp4 i/o i2c1_sda pf.4 mfp3 i/o i2c1 data input/output pin. pc.10 mfp3 i/o pe.0 mfp3 i/o pc.5 mfp3 i/o pe.5 mfp3 i/o p a.9 mfp 2 i/o pe.9 mfp4 i/o ice ice_clk pe.6 mfp1 i serial wired debugger clock pin. ice_dat pe.7 mfp1 o serial wired debugger data pin. int0 int0 pd.2 mfp8 i external interrupt 0 input pin. pe.4 mfp8 i pa.0 mfp8 i int1 int1 pd.3 mfp8 i external interrupt 1 input pin. pe.5 mfp8 i pb.0 mfp8 i int2 int2 pc.0 mfp8 i external interrupt 2 input pin. int3 int3 pd.0 mfp8 i external interrupt 3 input pin. int4 int4 pe.0 mfp8 i external interrupt 4 input pin. int5 int5 pf.0 mfp8 i external interrupt 5 input pin. pwm0 pwm0_brake0 pd.2 mfp6 i pwm0 brake 0 input pin. pd.4 mfp5 i pa.8 mfp7 i pwm0_brake1 pd.3 mfp6 i pwm0 brake 1 input pin. pd.5 mfp5 i pwm0_ch0 pc.0 mfp6 i/o pwm0 channel 0 output/capture input. pe.0 mfp6 i/o pwm0_ch1 pc.1 mfp6 i/o pwm0 channel 1 output/capture input. pe.1 mfp6 i/o pwm0_ch2 pc.2 mfp6 i/o pwm0 channel 2 output/capture input. pb.8 mfp6 i/o pe.2 mfp6 i/o pwm0_ch3 pe.3 mfp6 i/o pwm0 channel 3 output/capture input. pc.3 mfp6 i/o
nuc126 aug . 08 , 201 8 page 4 5 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pwm0_ch4 pc.4 mfp6 i/o pwm0 channel 4 output/capture input. pwm0_ch5 pd.6 mfp6 i/o pwm0 channel 5 output/capture input. pd.7 mfp6 i/o pc.5 mfp6 i/o pwm0_sync_in pd.1 mfp2 i pwm0 counter synchronous trigger input pin. pd.7 mfp3 i pwm0_sync_out pb.1 mfp6 o pwm0 counter synchronous trigger output pin. pwm1 pwm1_brake0 pf.1 mfp6 i pwm1 brake 0 input pin. pe.4 mfp6 i pwm1_brake1 pf.2 mfp6 i pwm1 brake 1 input pin. pe.5 mfp6 i pa.9 mfp7 i pwm1_ch0 pd.12 mfp6 i/o pwm1 channel 0 output/capture input. pc.9 mfp6 i/o pc.6 mfp6 i/o pwm1_ch1 pd.13 mfp6 i/o pwm1 channel 1 output/capture input. pc.10 mfp6 i/o pc.7 mfp6 i/o pb.12 mfp6 i/o pwm1_ch2 pd.14 mfp6 i/o pwm1 channel 2 output/capture input. pc.11 mfp6 i/o pa.3 mfp6 i/o pwm1_ch3 pd.15 mfp6 i/o pwm1 channel 3 output/capture input. pc.12 mfp6 i/o pa.2 mfp6 i/o pwm1_ch4 pc.13 mfp6 i/o pwm1 channel 4 output/capture input. pa.1 mfp6 i/o pwm1_ch5 pc.14 mfp6 i/o pwm1 channel 5 output/capture input. pa.0 mfp6 i/o sc0 sc0_clk pc.1 mfp2 o smart card 0 clock pin. pe.11 mfp5 o pa.0 mfp5 o sc0_dat pc.0 mfp1 i/o smart card 0 data pin. pe.10 mfp5 i/o
nuc126 aug . 08 , 201 8 page 46 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pa.1 mfp5 i/o sc0_pwr pc.3 mfp1 o smart card 0 power pin. pe.4 mfp5 o pe.8 mfp5 o pa.3 mfp5 o pa. 8 mfp 4 o sc0_rst pc.2 mfp1 o smart card 0 reset pin. pe.5 mfp5 o pe.9 mfp5 o pa.2 mfp5 o pb.1 mfp5 o pa. 9 mfp 4 o sc0_ncd pc.4 mfp1 i smart card 0 card detect pin. pe.0 mfp5 i pe.1 mfp5 i pb.2 mfp5 i sc1 sc1_clk pd.0 mfp6 o smart card 1 clock pin. sc1_dat pb.7 mfp6 i/o smart card 1 data pin. sc1_pwr pb.6 mfp6 o smart card 1 power pin. pa.9 mfp5 o sc1_rst pb.5 mfp6 o smart card 1 reset pin. pa.8 mfp5 o sc1_ncd pb.4 mfp6 i smart card 1 card detect pin. spi0 spi0_clk pb.7 mfp2 i/o spi0 serial clock pin. pc.12 mfp2 i/o pc.0 mfp2 i/o pe.0 mfp2 i/o pe.13 mfp2 i/o pb.2 mfp2 i/o spi0_i2smclk pd.0 mfp1 i/o spi0 i2s master clock output pin pd.3 mfp2 i/o pd.7 mfp2 i/o pc.9 mfp2 i/o pc.5 mfp2 i/o
nuc126 aug . 08 , 201 8 page 47 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description spi0_miso pb.6 mfp2 i/o spi0 miso (master in, slave out) pin. pc.11 mfp2 i/o pc.4 mfp2 i/o pe.10 mfp2 i/o pb.3 mfp2 i/o spi0_mosi pb.5 mfp2 i/o spi0 mosi (master out, slave in) pin. pc.10 mfp2 i/o pc.3 mfp2 i/o pe.11 mfp2 i/o spi0_ss pc.13 mfp2 i/o spi0 slave select pin. pc.2 mfp2 i/o pe.12 mfp2 i/o pb.4 mfp2 i/o spi1 spi1_clk pb.7 mfp3 i/o spi1 serial clock pin. pd.4 mfp2 i/o pd.15 mfp2 i/o pa.7 mfp2 i/o pe.10 mfp6 i/o pe.13 mfp1 i/o pb.2 mfp3 i/o spi1_i2smclk pd.0 mfp2 i/o spi1 i2s master clock output pin pa. 9 mfp 1 i/o pa.12 mfp2 i/o spi1_miso pb.6 mfp3 i/o spi1 miso (master in, slave out) pin. pd.5 mfp2 i/o pd.14 mfp2 i/o pa.6 mfp2 i/o pe.10 mfp1 i/o pe.11 mfp6 i/o pb.3 mfp3 i/o spi1_mosi pb.5 mfp3 i/o spi1 mosi (master out, slave in) pin. pe.3 mfp2 i/o pd.13 mfp2 i/o pa.5 mfp2 i/o
nuc126 aug . 08 , 201 8 page 48 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pe.11 mfp1 i/o pe.12 mfp6 i/o spi1_ss pd.6 mfp2 i/o spi1 slave select pin. pd.12 mfp2 i/o pa.4 mfp2 i/o pe.12 mfp1 i/o pe.13 mfp6 i/o pb.4 mfp3 i/o tm0 tm0 pd.1 mfp6 i/o timer0 event counter input/toggle output pin. pd.4 mfp6 i/o pe.8 mfp3 i/o tm0_ext pd.2 mfp3 i/o timer0 external capture input/toggle output pin. pa.7 mfp3 i/o pe.10 mfp8 i/o pb.3 mfp10 i/o \ tm1 tm1 pd.5 mfp6 i/o timer1 event counter input/toggle output pin. pd.7 mfp4 i/o pa. 8 mfp 8 i/o pe.9 mfp3 i/o tm1_ext pd.3 mfp3 i/o timer1 external capture input/toggle output pin. pa.6 mfp3 i/o pe.11 mfp8 i/o pb.0 mfp10 i/o pb.4 mfp10 i/o tm2 tm2 pd.8 mfp6 i/o timer2 event counter input/toggle output pin. pd.3 mfp1 i/o pd.10 mfp4 i/o pa.14 mfp6 i/o pa. 9 mfp 8 i/o pb.0 mfp4 i/o tm2_ext pe.0 mfp4 i/o timer2 external capture input/toggle output pin. pa.5 mfp3 i/o pe.12 mfp8 i/o pb.2 mfp10 i/o
nuc126 aug . 08 , 201 8 page 49 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description tm3 tm3 pd.9 mfp6 i/o timer3 event counter input/toggle output pin. pd.11 mfp4 i/o pa.15 mfp6 i/o pb.1 mfp4 i/o tm3_ext pa.4 mfp3 i/o timer3 external capture input/toggle output pin. pe.1 mfp3 i/o pe.13 mfp8 i/o tm tm_brake0 pa.8 mfp6 i timer brake 0 input pin. pb.2 mfp6 i tm_brake1 pa.9 mfp6 i timer brake 1 input pin. pa.7 mfp6 i pb.3 mfp6 i tm_brake2 pa.6 mfp6 i timer brake 2 input pin. pa.12 mfp6 i pb.8 mfp5 i tm_brake3 pa.5 mfp6 i timer brake 3 input pin. pa.13 mfp6 i pe.2 mfp5 i uart0 uart0_rxd pd.0 mfp3 i uart0 data receiver input pin. pd.9 mfp3 i pd.6 mfp3 i pd.13 mfp3 i pe.6 mfp3 i pa.3 mfp2 i uart0_txd pd.1 mfp3 o uart0 data transmitter output pin. pd.12 mfp3 o pe.7 mfp3 o pa.2 mfp2 o uart0_ncts pd.8 mfp3 i uart0 clear to send input pin. pd.14 mfp3 i pa.2 mfp3 i uart0_nrts pc.8 mfp3 o uart0 request to send output pin. pd.15 mfp3 o pa.3 mfp3 o
nuc126 aug . 08 , 201 8 page 50 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description uart1 uart1_rxd pa.9 mfp3 i uart1 data receiver input pin. pe.9 mfp1 i pe.13 mfp3 i pa.1 mfp3 i pa.12 mfp4 i pb.2 mfp4 i uart1_txd pa.8 mfp3 o uart1 data transmitter output pin. pe.8 mfp1 o pe.12 mfp3 o pa.0 mfp3 o pa.13 mfp4 o pb.3 mfp4 o uart1_ncts pe.10 mfp3 i uart1 clear to send input pin. pa.0 mfp1 i pb.4 mfp4 i uart1_nrts pe.11 mfp3 o uart1 request to send output pin. pa.1 mfp1 o pb.8 mfp4 o pe.2 mfp4 o uart2 uart2_rxd pe.3 mfp4 i uart2 data receiver input pin. pc.3 mfp3 i pa.12 mfp3 i pb.0 mfp3 i uart2_txd pd.6 mfp4 o uart2 data transmitter output pin. pc.2 mfp3 o pa.13 mfp3 o pb.1 mfp3 o pb. 4 mfp9 o pb.5 mfp9 o uart2_ncts pd.5 mfp4 i uart2 clear to send input pin. pc.0 mfp3 i pa.14 mfp3 i uart2_nrts pd.4 mfp4 o uart2 request to send output pin. pc.1 mfp3 o
nuc126 aug . 08 , 201 8 page 51 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pa.15 mfp3 o usci0 usci0_clk pc.4 mfp5 i/o usci0 clock pin. pe.5 mfp4 i/o pb.9 mfp8 i/o usci0_ctl0 pc.3 mfp5 i/o usci0 control 0 pin. pe.4 mfp4 i/o pb.8 mfp8 i/o pe.2 mfp8 i/o usci0_ctl1 pc.2 mfp4 i/o usci0 control 1 pin. pc.7 mfp4 i/o pb.4 mfp8 i/o usci0_dat0 pc.0 mfp4 i/o usci0 data 0 pin. pc.5 mfp4 i/o pb.2 mfp8 i/o usci0_dat1 pc.1 mfp4 i/o usci0 data 1 pin. pc.6 mfp4 i/o pb.3 mfp8 i/o usci1 usci1_clk pd.15 mfp1 i/o usci1 clock pin. pa.3 mfp8 i/o pa.15 mfp4 i/o usci1_ctl0 pd.12 mfp1 i/o usci1 control 0 pin. pa.2 mfp8 i/o pa.0 mfp4 i/o usci1_ctl1 pd.7 mfp1 i/o usci1 control 1 pin. pa.1 mfp4 i/o pa.14 mfp4 i/o usci1_dat0 pd.14 mfp1 i/o usci1 data 0 pin. pb.0 mfp6 i/o usci1_dat1 pd.13 mfp1 i/o usci1 data 1 pin. pb.1 mfp8 i/o usci2 usci2_clk pd.1 mfp4 i/o usci2 clock pin. pf.2 mfp5 i/o pc.11 mfp4 i/o usci2_ctl0 pd.0 mfp4 i/o usci2 control 0 pin.
nuc126 aug . 08 , 201 8 page 52 of 140 rev 1 .0 4 nuc126 series datasheet group pin name gpio mfp * type description pd.9 mfp4 i/o pf.1 mfp5 i/o pc.12 mfp4 i/o usci2_ctl1 pb.7 mfp4 i/o usci2 control 1 pin. pd.8 mfp4 i/o pf.0 mfp5 i/o pc.9 mfp4 i/o usci2_dat0 pd.2 mfp4 i/o usci2 data 0 pin. pd.10 mfp5 i/o pc.13 mfp4 i/o usci2_dat1 pd.3 mfp4 i/o usci2 data 1 pin. pd.11 mfp5 i/o pc.10 mfp4 i/o vdet vdet_p0 pb.0 mfp2 a voltage detector positive input 0 pin. vdet_p1 pb.1 mfp2 a voltage detector positive input 1 pin. x32 x32_in pf.1 mfp1 i external 32.768 khz crystal input pin. x32_out pf.0 mfp1 o external 32.768 khz crystal output pin. xt1 xt1_in pf.4 mfp1 i external 4~24 mhz (high speed) crystal input pin. xt1_out pf.3 mfp1 o external 4~24 mhz (high speed) crystal output pin. table 4.3 - 1 nuc126 gpio multi - function table
nuc126 aug . 08 , 201 8 page 53 of 140 rev 1 .0 4 nuc126 series datasheet 5 block diagram 5.1 numicro ? nuc126 block diagram figure 5.1 - 1 numicro ? nuc126 block diagram a r m c o r t e x - m 0 7 2 m h z m e m o r y a p r o m 2 5 6 / 1 2 8 k b a n a l o g i n t e r f a c e 1 2 - b i t a d c 2 0 - c h p o w e r c o n t r o l c l o c k c o n t r o l l d o 1 . 8 v p o r l v r b o r h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z l o w s p e e d c r y s t a l o s c . ( l x t ) 3 2 . 7 6 8 k h z l o w s p e e d o s c i l l a t o r ( l i r c ) 1 0 k h z p l l a n a l o g c o m p a r a t o r x 2 a h b b u s a p b b u s b r i d g e h i g h s p e e d c r y s t a l o s c . ( h x t ) 4 ~ 2 4 m h z r t c / p w m / t i m e r i / o p o r t s g e n e r a l p u r p o s e i / o e x t e r n a l b u s i n t e r f a c e e x t e r n a l i n t e r r u p t c o n n e c t i v i t y u a r t x 3 v r e f ( 2 . 0 4 8 v / 2 . 5 6 v / 3 . 0 7 2 v / 4 . 9 6 v ) h i g h s p e e d o s c i l l a t o r 4 8 m h z r t c ( v b a t ) l d r o m 4 k b d a t a f l a s h c o n f i g u r a b l e s r a m 2 0 k b s p r o m 2 k b s p e e d u p p d m a - 5 c h h a r d d i v i d e r c r c w a t c h d o g t i m e r t i m e r / p w m x 4 p w m 1 2 - c h s p i / i 2 s x 2 i 2 c x 2 i s o - 7 8 1 6 - 3 x 2 u s c i x 3 u s b 2 . 0 f s
nuc126 aug . 08 , 201 8 page 54 of 140 rev 1 .0 4 nuc126 series datasheet 6 functional descripti on 6.1 arm ? cortex ? - m 0 core the cortex ? - m0 processor is a configurable, multistage, 32 - bit risc processor, which has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex ? - m profile processor. the profile supports two modes C thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a resul t of an exception return. figure 6.1 - 1 shows the functional controller of processor. figure 6.1 - 1 functional block diagram the implemented device provides: ? a low gate count processor: C armv6 - m thumb? instruction set C thumb - 2 technology C armv6 - m compliant 24 - bit systick timer C a 32 - bit hardware multiplier C system interface supported with little - endian data accesses C ability to have deterministic, fixed - latency, interrupt handling C load/store - multiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling C c application binary inter face compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers C low power sleep mode entry using the wait for interrupt (wfi), wait for eve nt (wfe) instructions, or return from interrupt sleep - on - exit feature c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
nuc126 aug . 08 , 201 8 page 55 of 140 rev 1 .0 4 nuc126 series datasheet ? nvic: C 32 external interrupt inputs, each with four levels of priority C dedicated non - maskable interrupt (nmi) input C supports for both level - sensitive and pulse - sensitive interrupt lines C supports wake - up interrupt controller (wic) and, providing ultra - low power sleep mode ? debug support: C four hardware breakpoints C two watchpoints C program counter sampling register (pcsr) for non - intrusive code profiling C single step and vector catch capabiliti es ? bus interfaces: C single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory C single 32 - bit slave port that supports the dap (debug access port)
nuc126 aug . 08 , 201 8 page 56 of 140 rev 1 .0 4 nuc126 series datasheet 6.2 system manager 6.2.1 overview the system manager provides the functions of system control, power modes, wake - up sources, reset sources , system memory map , product id and multi - function pin control . the following sections describe the functions for ? system reset ? power modes and wake - up sources ? system power distributio n ? sram memory organization ? system control r egister for part number id, c hip r eset and m ulti - function p in c ontrol ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control register 6.2.2 system reset the system reset can be issued by one of the events listed below . the se reset event flags can be read from sys_rststs register to determine the reset source . hardware reset sourcces are from peripheral signals. software reset can trigger reset through setting control registers. ? h ardware reset sources C power - on reset (por) C low level on the nreset pin C watchdog time - out reset and window watchdog reset (wdt/wwdt reset) C low voltage reset (lvr) C brown - out detector reset (bod reset) C cpu lockup reset ? software reset sources C chip reset will reset whole chip by writing 1 to chiprst (sys_iprst0[0]) C mcu reset to reboot but keeping the booting setting from aprom or ldrom by writing 1 to sysresetreq (aircr[2]) C cpu reset for cortex ? - m 0 core only by writing 1 to cpurst (sys_iprst0[1 ])
nuc126 aug . 08 , 201 8 page 57 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 1 system reset s ources l o w v o l t a g e r e s e t p o w e r - o n r e s e t b r o w n - o u t r e s e t r e s e t p u l s e w i d t h ~ 3 . 2 m s w d t / w w d t r e s e t s y s t e m r e s e t ~ 5 0 k o h m @ 5 v r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s n r e s e t v d d a v d d c h i p r e s e t c h i p r s t ( s y s _ i p r s t 0 [ 0 ] ) c p u r e s e t c p u r s t ( s y s _ i p r s t 0 [ 1 ] ) c p u l o c k u p r e s e t m c u r e s e t s y s r s t r e q ( a i r c r [ 2 ] ) l v r e n ( s y s _ b o d c t l [ 7 ] ) b o d r s t e n ( s y s _ b o d c t l [ 3 ] ) p o r o f f ( s y s _ p o r c t l [ 1 5 : 0 ] ) r e s e t p u l s e w i d t h 6 4 w d t c l o c k s r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s g l i t c h f i l t e r ~ 3 6 u s s o f t w a r e r e s e t r e s e t c o n t r o l l e r
nuc126 aug . 08 , 201 8 page 58 of 140 rev 1 .0 4 nuc126 series datasheet there are a total of 9 reset sources in the numicro ? family. in general, cpu reset is used to reset cortex ? - m 0 only; the other reset sources will reset cortex ? - m 0 and all peripherals. however, there are small differences between each reset source and they are listed in table 6.2 - 1 . reset so urces register por n reset wdt lvr bod lockup chip mcu cpu sys_rststs 0x01 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 8 = 1 bit 0 = 1 bit 5 = 1 bit 7 = 1 chiprst (sys_iprst0[0]) 0x0 - - - - - - - - boden (sys_bodctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 reload from config0 reload from config0 - bodvl (sys_bodctl[2:1]) bodrsten (sys_bodctl[3]) hxten (clk_pwrctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 lxten (clk_pwrctl[1]) 0x0 - - - - - - - - wdtcken (clk_apbclk0[0]) 0x1 - 0x1 - - - 0x1 - - hclksel (clk_clksel0[2:0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdtsel (clk_clksel1[1:0]) 0x3 0x3 - - - - - - - hxtstb (clk_status[0]) 0x0 - - - - - - - - lxtstb (clk_status[1]) 0x0 - - - - - - - - pllstb (clk_status[2]) 0x0 - - - - - - - - hircstb (clk_status[4]) 0x0 - - - - - - - - clksfail (clk_status[7]) 0x0 0x0 - - - - - - - rsten (wdt_ctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - wdten (wdt_ctl[7]) wdt_ctl except bit 1 and bit 7. 0x0700 0x0700 0x0700 0x0700 0x0700 - 0x0700 - -
nuc126 aug . 08 , 201 8 page 59 of 140 rev 1 .0 4 nuc126 series datasheet wdt_altctl 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_rldcnt 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_ctl 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 - 0x3f0800 - - wwdt_status 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_cnt 0x3f 0x3f 0x3f 0x3f 0x3f - 0x3f - - bs (fmc_ispctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - bl (fmc_ispctl[16]) fmc_dfba reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 - reload from config1 - - cbs (fmc_ispsts[2:1 ]] reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - vecmap (fmc_ispsts[23:9]) reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 - reload base on config0 - - other peripheral registers reset value - fmc registers reset value note: - means that the value of register keeps original setting. table 6.2 - 1 reset value of registers 6.2.2.1 nreset reset the nreset reset means to generate a reset signal by pull ing low nreset pin , which is an asynchronous reset input pin and can be used to reset system at any time. when the nreset voltage is lower than 0.2 v dd and the state keeps longer than 36 us (glitch filter ), c hip will be reset. the nreset reset will control the chip in reset state until the nreset voltage rises above 0.7 v dd and the state keeps longer than 36 us ( glitch filter). the pinrf(sys_rststs[1]) will be set to 1 if the previous reset source is nreset reset. figure 6.2 - 2 shows the nreset reset waveform. figure 6.2 - 2 nreset reset w aveform n r e s e t 0 . 2 v d d 0 . 7 v d d n r e s e t r e s e t 3 6 u s 3 6 u s
nuc126 aug . 08 , 201 8 page 60 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.2.2 power - o n reset (por) the power - on reset (por) is used to generate a stable system reset signal and forces the system to be reset when p ower - on to avoid unexpected behavior of mcu. when applying the power to mcu, the por module will detect the rising voltage and generate reset signal to system until the voltage is ready for mcu operation. at por reset, the porf(sys_rststs[0]) will be set to 1 to indicate there is a por reset event. the porf(sys_rststs[0]) bit can be cleared by writing 1 to it . figure 6.2 - 3 shows the p ower - o n reset waveform. figure 6.2 - 3 power - o n reset (por) w aveform 6.2.2.3 low voltage reset (lvr) if the low voltage reset function is enabled by setting the low voltage reset enable bit lvren (sys_bodctl[7]) to 1, after 200us delay, lvr detection circuit will be stable and the lvr function will be active. then lvr function will detect av dd during system operation. when the av dd voltage is lower than v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]) , c hip will be reset. the lvr reset will control the chip in reset state until the av dd voltage rises above v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]). the default setting of low voltage reset is enabled without de - g litch function. figure 6.2 - 4 shows the low voltage reset waveform. v d d v p o r p o w e r - o n r e s e t 0 . 1 v
nuc126 aug . 08 , 201 8 page 61 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 4 low voltage reset (lvr) w aveform 6.2.2.4 brown - out detector reset (bod reset) if the brown - o ut detector (bod) function is enabled by setting the brown - o ut detector enable bit boden (sys_bodctl[0]), brown - o ut detector function will detect av dd during system operation. when the av dd voltage is lower than v bod which is decided by boden (sys_bodctl[0]) and bodvl (sys_bodctl[2:1]) and the state keeps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]) , c hip will be reset. the bod reset will control the chip in reset state until the av dd voltage rises above v bod and the state kee ps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]). the default value of boden, bodvl and bodrsten (sys_bodctl[3]) is set by flash controller user configuration register cboden (config0 [23]), cbov (config0 [22:21]) and cborst(config0[20]) re spectively. user can determine the initial bod setting by setting the config0 register. figure 6.2 - 5 shows the brown - o ut detector waveform . a v d d v l v r l o w v o l t a g e r e s e t t 1 ( < l v r d g s e l ) t 2 ( = l v r d g s e l ) t 3 ( = l v r d g s e l ) l v r e n 2 0 0 u s d e l a y f o r l v r s t a b l e
nuc126 aug . 08 , 201 8 page 6 2 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 5 brown - o ut detector (bod) w aveform 6.2.2.5 watch d og timer reset (wdt) in most industr ial applications, system reliability is very important. to automatically recover the mcu from failure status is one way to improve system reliability. the watchdog timer(wdt) is widely used to check if the system works fine. if the mcu is cr ashed or out of control, it may cause the watchdog time - out. user may decide to enable system reset during watchdog time - out to recover the system and take action for the system crash/out - of - control after reset. software can check if the reset is caused b y watchdog time - out to indicate the previous reset is a watchdog reset and handle the failure of mcu after watchdog time - out reset by checking wdtrf(sys_rststs[2]). 6.2.2.6 cpu lockup reset cpu enters lockup status after cpu produces hardfault at hardfault handle r and chip gives immediate indication of seriously errant kernel software. this is the result of the cpu being locked because of an unrecoverable exception following the activation of the processors built in system state protection hardware. when chip ent ers debug mode, the cpu lockup reset will be ignored. 6.2.2.7 cpu reset, chip reset and mcu reset the cpu reset means only cortex ? - m 0 core is reset and all other peripherals remain the same status after cpu r eset. user can set the cpurst(sys_iprst0[1]) to 1 to ass ert the cpu reset signal. the chip reset is same with power - o n reset. the cpu and all peripherals are reset and bs(fmc_ispctl[1]) bit is automatically reloaded from config 0 setting. user can set the chiprst(sys_iprst0[1]) to 1 to assert the chip reset sign al. a v d d v b o d l b o d o u t b o d r s t e n b r o w n - o u t r e s e t t 1 ( < b o d d g s e l ) t 2 ( = b o d d g s e l ) t 3 ( = b o d d g s e l ) h y s t e r e s i s v b o d h
nuc126 aug . 08 , 201 8 page 63 of 140 rev 1 .0 4 nuc126 series datasheet the mcu reset is similar with chip reset. the difference is that bs(fmc_ispctl[1]) will not be reloaded from config 0 setting and keep its original software setting for booting from aprom or ldrom . user can set the sysresetreq(aircr[2]) to 1 to assert t he mcu reset. 6.2.3 power m odes and wake - up s ources there are several wake - up sources in i dle mode and p ower - down mode. table 6.2 - 2 lists the available clocks for each power mode. power mode normal m ode idle m ode power - down m ode definition cpu is in active state cpu is in sleep state cpu is in sleep state and all clocks stop except lxt and lirc. sram content retended. entry condition c hip is in normal mode after system reset released cpu executes wfi instruction. cpu sets sleep mode enable and power down enable and executes wfi instruction. wake - up sources n/a all in terrupts rtc, wdt, i2c, timer, uart, bod, gpio, eint , usci, usbd , acmp and vdet . available clocks all all except cpu clock lxt and lirc after wake - up n/a cpu back to normal mode cpu back to normal mode table 6.2 - 2 power mode difference table
nuc126 aug . 08 , 201 8 page 64 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 6 numicro ? nuc126 power mode state machine 1. lxt (32 768 hz xtl) on or off depend s on sw setting in normal mode . 2. lirc (10 khz osc) on or off depend s on s/w setting in normal mode . 3 . if timer clock source is selected as lirc/lxt and lirc/lxt is on. 4 . if wdt clock source is selected as lirc and lirc is on. 5 . if rtc clock source is selected as lxt and lxt is on. 6 . if uart clock source is selected as lxt and lxt is on. normal mode idle mode power - down mode hxt (4~20 mhz xtl) on on halt hirc ( 22.1184 mhz osc) on on halt hirc48 (48 mhz osc) on on halt lxt (32 768 hz xtl) on on on/off 1 lirc (10 khz osc) on on on/off 2 pll on on halt ldo on on on cpu on halt halt hclk/pclk on on halt sram retention on on on flash on on halt gpio on on halt p dma on on halt t i m e r on on on/off 3 pwm on on halt wdt on on on/off 4 n o r m a l m o d e c p u c l o c k o n p o w e r - d o w n m o d e c p u c l o c k o f f h x t , h i r c , h i r c 4 8 , p c l k o f f f l a s h h a l t s y s t e m r e s e t r e l e a s e d c p u e x e c u t e s w f i i n t e r r u p t s o c c u r i d l e m o d e c p u c l o c k o f f f l a s h h a l t 1 . s l e e p d e e p ( s c r [ 2 ] ) = 1 2 . p d e n ( c l k _ p w r c t l [ 7 ] ) = 1 3 . c p u e x e c u t e s w f i w a k e - u p e v e n t s o c c u r l x t , l i r c o n h x t , h i r c , h i r c 4 8 , p c l k o f f l x t , l i r c o n h x t , h i r c , h i r c 4 8 , l x t , l i r c , h c l k , p c l k o n f l a s h o n
nuc126 aug . 08 , 201 8 page 65 of 140 rev 1 .0 4 nuc126 series datasheet wwdt on on halt rtc on on on/off 5 uart on on on/off 6 sc on on halt usci on on halt i 2 c on on halt spi on on halt usb d on on halt adc on on halt acmp on on halt table 6.2 - 3 clocks in power modes wake - up sources in power - down mode : rtc, wdt, i2c, timer, uart, usci, bod, vdet , gpio, usbd, and acmp . after chip enters power down, the following wake - up sources can wake chip up to n ormal mode . table 6.2 - 4 list s the condition about how to enter p ow er - down mode again for each peripheral. *user needs to wait this condition before setting pden( clk_ pwrctl[ 7 ]) and execute wfi to enter power - down mode. wake - up source wake - up condition system can enter power - down mode again condition * bod brown - out detector interrupt after software writes 1 to clear bodif (sys_bodctl[4]). vdet voltage detector interrupt after software writes 1 to clear vdet if (sys_bodctl[19]). gpio gpio interrupt after software write 1 to clear the px_ intsrc [n] bit. timer timer interrupt after software writes 1 to clear twkf ( timer x _intsts [1]) and t i f ( timer x _intsts [0]) . wdt wdt interrupt after software writes 1 to clear wkf ( wdt_ctl [5]) (write protect). rtc alarm interrupt after software writes 1 to clear almif (rtc_intsts[0]) . time tick interrupt after software writes 1 to clear tickif (rtc_intsts[1]) . uart ncts wake - up a fter software writes 1 to clear ctswkf ( uart x _ wk sts [0]) . rx data wake - up a fter software writes 1 to clear datwkf ( uart x _ wk sts [1]). received fifo threshold wake - up a fter software writes 1 to clear rfrt wkf ( uart x _ wk sts [2]). rs - 485 aad mode wake - up a fter software writes 1 to clear rs485 wkf ( uart x _ wk sts [3]). received fifo threshold time - out wake - up a fter software writes 1 to clear tout wkf ( uart x _ wk sts [4]). usci uart cts toggle after software writes 1 to clear wkf (uuart_wksts[0]).
nuc126 aug . 08 , 201 8 page 66 of 140 rev 1 .0 4 nuc126 series datasheet data toggle after software writes 1 to clear wkf (uuart_wksts[0]). usci i 2 c data toggle after software writes 1 to clear wkf (ui2c_wksts[0]). address match after software writes 1 to clear wkakdone (ui2c_protsts[16], then writes 1 to clear wkf (ui2c_wksts[0]). usci sp i ss toggle after software writes 1 to clear wkf (uspi_wksts[0]). i 2 c address match wake - up a fter software writes 1 to clear wkakdone (i2c_wksts[1]). then software writes 1 to clear wkif(i2c_wksts[0]). usb d remote wake - up after software writes 1 to clear busif ( usbd_intsts [0]). acmp comparator power - down wake - up interrupt after software writes 1 to clear wkif0 (acmp_status[8]) and wkif1 (acmp_status[9]). table 6.2 - 4 condition of entering power - down mode again 6.2.4 system power distribution in this chip, power distribution is divided into four segments : ? analog power from av dd and av ss provides the power for analog components operation. the v ref should be connected with an external 1uf capacitor that should be located close to the v ref pin to avoid power noise for analog applications. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from v bus offers the power for operating the usb transceiver. ? rtc power from v bat provides the power for rtc. ? a dedicated power from v ddio supplies the power for p e.8 ~ p e .1 3. the outputs of internal voltage regulators, ldo and vdd33, require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 6.2 - 7 shows the power distribution of the nuc126 series .
nuc126 aug . 08 , 201 8 page 67 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 7 numicro ? nuc126 power distribution diagram u s b t r a n s c e i v e r a v d d a v s s v d d v s s v b u s u s b _ d + u s b _ d - v b a t 5 v t o 3 . 3 v l d o i o c e l l v d d t o 1 . 8 v l d o p o r 5 0 4 ~ 2 4 m h z c r y s t a l o s c i l l a t o r 3 2 . 7 6 8 k h z c r y s t a l o s c i l l a t o r r t c p o w e r o n c o n t r o l x 3 2 _ i n ( p f . 1 ) x 3 2 _ o u t ( p f . 0 ) v r e f x t 1 _ o u t x t 1 _ i n 1 . 8 v 3 . 3 v u s b _ v d d 3 3 _ c a p 1 u f v d d i o i o c e l l p e . 8 ~ p e . 1 3 v b a t t o 1 . 8 v l d o i o c e l l b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t 1 2 - b i t a d c i n t e r n a l r e f e r e n c e v o l t a g e a n a l o g c o m p a r a t o r p f . 2 1 u f 2 2 . 1 1 8 4 m h z h i r c o s c i l l a t o r 1 0 k h z l i r c o s c i l l a t o r s r a m p l l p o r 1 8 t e m p e r a t u r e s e n s o r d i g i t a l l o g i c f l a s h 1 . 8 v l d o _ c a p 1 u f 4 8 m h z h i r c 4 8 o s c i l l a t o r
nuc126 aug . 08 , 201 8 page 68 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.5 system memory map the nuc126 s eries provides 4g - byte addressing space. the memory locations assigned to each on - chip controllers are shown in table 6.2 - 5 . the detailed register defi nition, memory space, and programming will be described in the following sections for each on - chip peripheral. the nuc126 s eries only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x000 1 _ffff flash_ba flash memory space ( 128 kb) 0x0000_0000 C 0x0003_ffff flash_ba flash memory space (256 kb) 0x0004_0000 C 0x0005_ffff reserved reserved 0x0006_0000 C 0x0007_ffff reserved reserved 0x2000_0000 C 0x2000_4fff sram_ba sram memory space (20 kb) 0x2000_4000 C 0x2000_bfff reserved reserved 0x2000_c000 C 0x2000_ffff reserved reserved 0x6000_0000 C 0x601f_ffff extmem_ba external memory space for ebi interface (2 mb) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff sys_ba system control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 C 0x5001_03ff ebi_ba ebi control registers 0x5001_4000 C 0x5001_7fff hdiv_ba hardware divider registers 0x5001_8000 C 0x5001_ffff crc_ba crc generator registers peripheral controllers space (0x4000_0000 C 0x401f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwm0_ba pwm0 control registers 0x4004_4000 C 0x4004_7fff reserved reserved 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x4007_0000 C 0x4007_3fff usci0_ba usci0 control registers
nuc126 aug . 08 , 201 8 page 69 of 140 rev 1 .0 4 nuc126 series datasheet 0x4007_4000 C 0x4007_7fff usci2_ba usci2 control registers 0x400d_0000 C 0x400d_3fff acmp01_ba analog comparator control registers 0x400d_4000 C 0x400d_7fff reserved reserved 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers 0x4010_0000 C 0x4010_3fff reserved reserved 0x4011_0000 C 0x4011_3fff tmr23_ba timer2/timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4014_0000 C 0x4014_3fff pwm1_ba pwm1 control registers 0x4014_4000 C 0x4014_7fff reserved reserved 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x4015_4000 C 0x4015_7fff uart2_ba uart2 control registers 0x4017_0000 C 0x4017_3fff usci1_ba usci1 control registers 0x4017_4000 C 0x4017_7fff reserved reserved 0x4019_0000 C 0x4019_3fff sc0_ba sc0 control registers 0x4019_4000 C 0x4019_7fff sc1_ba sc1 control registers 0x401a_0000 C 0x401a_3fff reserved reserved system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers table 6.2 - 5 address space assignments for on - chip controllers
nuc126 aug . 08 , 201 8 page 70 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.6 sram memory orginization the nuc126 supports embedded sram with total 20 kbytes size in one bank. ? supports total 20 kbytes sram ? supports byte / half word / word write ? supports oversize response error figure 6.2 - 8 sram block diagram figure 6.2 - 9 shows the sram organization of nuc126 . there is one sram bank in the nuc126 and addressed to 20 kbytes. the address space is from 0x2000_0000 to 0x2000_4fff. the address between 0x2000_5000 t o 0x3fff_ffff is illegal memory space and chip will enter hardfault if cpu accesses these illegal memory addresses. a h b b u s s r a m b a n k s r a m d e c o d e r a h b i n t e r f a c e c o n t r o l l e r
nuc126 aug . 08 , 201 8 page 71 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.2 - 9 sram memory o rganization 6.2.7 register lock some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. these system control registers are protected after the power - on reset till user to disable register protection. for user to program these protected registers, a register protection disable sequence needs to be followed by a special programming. the register protection disable sequence is writing the data 59h, 16h 88h to the register sys_reglctl address at 0x 5 000_0100 continuously. any different data value, different sequence or any other write to other address during these three data writing will abort the whole sequence. after the protection is disabled, user can check the protection disable bit at address 0x 5 000_0100 bit0, 1 is protection disa ble, and 0 is protection enable. then user can update the target protected register value and then write any data to the address 0x 5 000_0100 to enable register protection. 6.2.8 auto trim this chip supports auto - trim function: the hirc trim (48 mhz and 22.1184 mhz rc oscillator), 5 1 2 m b 2 0 k b y t e s r a m b a n k 0 0 x 2 0 0 0 _ 0 0 0 0 r e s e r v e d 0 x 3 f f f _ f f f f 0 x 2 0 0 0 _ 4 f f f 0 x 2 0 0 0 _ 5 0 0 0 2 0 k b y t e d e v i c e
nuc126 aug . 08 , 201 8 page 72 of 140 rev 1 .0 4 nuc126 series datasheet according to the accurate external 32.768 khz crystal oscillator or internal usb synchronous mode, automatically gets accurate hirc output frequency, 0.25 % deviat ion within all temperature ranges. for instanc e, the system needs an accurate 22.1184 mhz clock. in such case, if users do not want to use pll as the system clock source, they need to solder 32.768 khz crystal in system, and set freqsel (sys_irctctl 0 [ 1: 0] trim frequency selection) to 0 1 , set refcksel (sys_irctctl0[9] reference clock selection) to 0 , and the auto - trim function will be enabled. interrupt status bit freqlock (sys_irctists[0] hirc frequency lock status) 1 indicates the hirc 0 output frequ ency is accurate within 0.25 % deviation. to get better results, it is recommended to set both loopsel (sys_irctctl[5:4] trim calculation loop) and retrycnt (sys_irctctl[7:6] trim value update limitation count) to 11 . a nother example is that the system ne eds an accurate 48 mhz clock for usb application. i n such case, if neither using use pll as the system clock source nor soldering 32.768 khz crystal in system, user has to set refck sel (sys_irctctl 1 [ 10 ] reference clock selection) to 1 , set freqsel (sys_i rctctl 1 [ 1: 0] trim frequency selection) to 10 , and the auto - trim function will be enabled. interrupt status bit freqlock 1 (sys_irctists[ 8 ] hirc frequency lock status) 1 indicates the hirc 1 output frequency is accurate within 0.25 % deviation. 6.2.9 uart1_txd modulation with pwm th is chip supports uart1_txd to modulate with pwm channel. user can set modpwmsel(sys_modctl[6:4]) to choice which pwm0 channel to modulate with uart1_txd and set moden(sys_modctl[0]) to enable modulation function. user can set txdinv(u art_line[8]) to inverse uart1_txd before moulating with pwm. figure 6.2 - 10 uart1_txd modulated with pwm channel p w m 0 _ c h x u a r t 1 _ t x d t x d i n v = 0 & m o d h = 0 t x d i n v = 0 & m o d h = 1 t x d i n v = 1 & m o d h = 0 t x d i n v = 1 & m o d h = 1
nuc126 aug . 08 , 201 8 page 73 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.10 voltage detector ( vdet ) this chip supports low power comparator to detect external voltage. user can control bandgap active interval and comparator active interval to achieve low power detection purpose. there is no debounce function in p ower - down mode since no hclk available in p ower - down mode. figure 6.2 - 11 vdet block diagram b a n d g a p 0 1 1 . 2 v v d e t p i n s e l ( s y s _ b o d c t l [ 1 7 ] ) v d e t _ p 0 v d e t _ p 1 v d e t o u t ( s y s _ b o d c t l [ 2 4 ] ) v d e t e n ( s y s _ b o d c t l [ 1 6 ] ) d e - g l i t c h v d e t d g s e l ( s y s _ b o d c t l [ 2 7 : 2 5 ] ) v d e t e n ( s y s _ b o d c t l [ 1 6 ] )
nuc126 aug . 08 , 201 8 page 74 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.11 system timer (systick) the cortex ? - m0 includes an integrated system timer, systick, which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the s ystick current value register (syst_cvr) to 0, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, then decrement on subsequent clocks. when the counter transitions to 0, the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc126 aug . 08 , 201 8 page 75 of 140 rev 1 .0 4 nuc126 series datasheet 6.2.12 nested vectored interrupt controller (nvic) the cortex ? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic), which is closely coupled to the processor kernel and provides following features: ? nested and vectored interrupt support ? automatic processor state saving and restoration ? reduced and deterministic interrupt late ncy the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptio ns can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interru pt handler will override the current handler. when an interrupt is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the s tarting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the men tioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before th e current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual. 6.2.12.1 exception model and system interrupt map table 6.2 - 6 lists the exception model supported by the nuc126 series. software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable prio rity is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable interrupts is 0. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception type vector number vector address priority reset 1 0x00000004 - 3 nmi 2 0x00000008 - 2 hard fault 3 0x0000000c - 1 reserved 4 ~ 10 reserved svcall 11 0x0000002c configurable reserved 12 ~ 13 reserved pendsv 14 0x00000038 configurable
nuc126 aug . 08 , 201 8 page 76 of 140 rev 1 .0 4 nuc126 series datasheet table 6.2 - 6 exception model vector number interrupt number ( bit in interrupt registers ) interrupt name interrupt description 0 ~ 15 - - system exceptions 16 0 bod_int brown - out low voltage detected interrupt 17 1 wdt_int window watchdog timer interrupt 18 2 eint024 external interrupt from pa . 0/pc . 0/pd . 2/pe . 0/pe . 4 pin 19 3 eint135 external interrupt from pb . 0/pc . 0/ pd . 0/pd . 3/pe . 5/pf . 0 pin 20 4 gpab_int external signal interrupt from pa[15:0]/pb[13:0] 21 5 gpcdef_int external interrupt from pc[15:0]/pd[15:0]/pe[13:0]/pf[7:0] 22 6 pwm0_int pwm0 interrupt 23 7 pwm1_int pwm1 interrupt 24 8 tmr0_int timer 0 interrupt 25 9 tmr1_int timer 1 interrupt 26 10 tmr2_int timer 2 interrupt 27 11 tmr3_int timer 3 interrupt 28 12 uart02_int uart0 and uart2 interrupt 29 13 uart1_int uart1 interrupt 30 14 spi0_int spi0 interrupt 31 15 spi1_int spi1 interrupt 32 16 reserved 33 17 reserved 34 18 i2c0_int i 2 c0 interrupt 35 19 i2c1_int i 2 c1 interrupt 36 20 reserved 37 21 reserved 38 22 usci_int usci0, usci1 and usci2 interrupt 39 23 usbd_int usb device interrupt 40 24 sc_int sc0 and sc1 interrupt 41 25 acmp01_int analog comparator interrupt systick 15 0x0000003c configurable interrupt (irq0 ~ irq) 16 ~ 47 0x00000000 + (vector number)*4 configurable
nuc126 aug . 08 , 201 8 page 77 of 140 rev 1 .0 4 nuc126 series datasheet 42 26 pdma_int pdma interrupt 43 27 reserved 44 28 pwrwu_int clock controller interrupt for chip wake - up from power - down state 45 29 adc_int adc interrupt 46 30 clkdirc_int clock fail detect and irc trim interrupt 47 31 rtc_int real time clock interrupt table 6.2 - 7 interrupt number table 6.2.12.2 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the en able bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respect ively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic in terrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
nuc126 aug . 08 , 201 8 page 78 of 140 rev 1 .0 4 nuc126 series datasheet 6.3 clock controller 6.3.1 overview the clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clock source selection and a clock divider. the chip will not enter p ower - down mode until cpu sets the p ower - down enable bit pden (clk_pwrctl[7]) and cortex ? - m 0 core executes the wfi instruction. after that, chip enters power - down mode and w ait for wake - up interrupt source triggered to leave power - down mode. in power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal (hxt), internal 22.1184 mhz internal high speed rc oscillator (hirc) and 4 8 mhz internal high s peed rc oscillator (hirc48) to reduce the overall system power consumption. figure 6.3 - 1 show s the clock generator and the overview of the clock source control. the clock generator consists of 6 clock sources, which are listed below: ? 32.768 khz external low - speed crystal oscilla tor ( l xt) ? 4~24 mhz external high speed crystal oscillator (hxt) ? programmable pll output clock frequency ( pllfout ), pll source can be selected from external 4~24 mhz external high speed crystal (hxt) or 22.1184 mhz internal high speed oscillator (hirc) ? 22.1184 mhz internal high speed rc oscillator (hirc) ? 4 8 mhz internal high speed rc oscillator (hirc 48 ) ? 10 khz internal low speed rc oscillator (lirc) each of these clock sources has certain stable time to wait for clock operating at stable frequency. when clock source is enabled, a stable counter start counting and correlated clock stable index (hircstb(clk_status[4]), lircstb(clk_status[3]), pllstb(clk_status[2]), hxtstb(clk_status[0]), lxtstb(clk_status[1]) and hirc48stb(clk_status[5])) are set to 1 aft er stable counter value reach a define value as shown in table 6.3 - 8 . system and peripheral can use the clock as its operating clock only when correla te clock stable index is set to 1. the clock stable index will auto clear when user disables the clock source (lircen(clk_pwrctl[3]), hircen(clk_pwrctl[2]), hxten(clk_pwrctl[0]), pd(clk_pllctl[16]), lxten(clk_pwrctl[1]) and hirc48en(clk_pwrctl[13])). besi des, the clock stable index of hxt, hirc and pll will auto clear when chip enter power - down and clock stable counter will re - counting after chip wake - up if correlate clock is enabled.
nuc126 aug . 08 , 201 8 page 7 9 of 140 rev 1 .0 4 nuc126 series datasheet clock source clock stable count value clock stable t ime hxt 4096 hxt clock 341.33 us for 12 mhz pll i ts based on the value of stbsel (clk_pllctl[23]) stbsel = 0, stable count is 6144 clocks of pll clock source. stbsel = 1, stable count is 12288 clocks of pll clock source. (default) stbsel = 0, 512 us for 512 mhz stbsel = 1, 1024 us for 12 mhz hirc48 512 h irc 48 clock 10.67 us for 48 mhz hirc 256 hirc clock 11.574 us for 22.1184 mhz lirc 1 lirc clock 100 us for 10 khz lxt 1 l xt clock 30.51 us for 32.768 khz table 6.3 - 8 clock stable count value table note: before clock switching, both the pre - selected and newly selected clock source must be turned on and stable. figure 6.3 - 1 clock g enerator b lock d iagram x t 1 _ o u t e x t e r n a l 4 ~ 2 4 m h z c r y s t a l ( h x t ) h x t e n ( c l k _ p w r c t l [ 0 ] ) x t 1 _ i n i n t e r n a l 2 2 . 1 1 8 4 m h z o s c i l l a t o r ( h i r c ) h i r c e n ( c l k _ p w r c t l [ 2 ] ) 0 1 p l l p l l s r c ( c l k _ p l l c t l [ 1 9 ] ) p l l f o u t x 3 2 _ o u t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l ( l x t ) l x t l x t e n ( c l k _ p w r c t l [ 1 ] ) x 3 2 _ i n i n t e r n a l 1 0 k h z o s c i l l a t o r ( l i r c ) l i r c e n ( c l k _ p w r c t l [ 3 ] ) h x t h i r c l i r c i n t e r n a l 4 8 m h z o s c i l l a t o r ( h i r c 4 8 ) l i r c e n ( c l k _ p w r c t l [ 1 3 ] ) h i r c 4 8
nuc126 aug . 08 , 201 8 page 80 of 140 rev 1 .0 4 nuc126 series datasheet note: before clock switching, both the pre - selected and newly selected clock source must be turned on and stable. figure 6.3 - 2 clock g enerator g lobal v iew d iagram c l k _ p l l c t l [ 1 9 ] c l k _ p l l c t l [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z p l l f o u t 4 ~ 2 4 m h z 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 4 ~ 2 4 m h z h c l k h c l k 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z 1 / 2 1 / 2 1 / 2 c l k _ c l k s e l 0 [ 5 : 3 ] s y s t i c k t m r 3 u a r t 0 - 2 p d m a u s c i 1 i 2 c 1 r t c f m c w d t p w m 1 p w m 0 t m r 0 t m r 1 t m r 2 c p u 3 2 . 7 6 8 k h z 1 0 k h z p c l k p c l k 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 4 ~ 2 4 m h z p l l f o u t p l l f o u t 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 4 ~ 2 4 m h z 1 0 k h z 1 0 k h z c l k _ c l k s e l 0 [ 2 : 0 ] s y s t _ c s r s y s t _ c s r c p u c l k c p u c l k 1 / ( h c l k d i v + 1 ) p c l k 1 c p u c l k h c l k 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z c l k _ c l k s e l 1 [ 1 0 : 8 ] c l k _ c l k s e l 1 [ 1 4 : 1 2 ] c l k _ c l k s e l 1 [ 1 8 : 1 6 ] c l k _ c l k s e l 1 [ 2 2 : 2 0 ] p l l f o u t p l l f o u t p c l k p c l k c l k _ c l k s e l 1 [ 2 8 ] c l k _ c l k s e l 1 [ 2 9 ] 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z 1 0 k h z 1 0 k h z 1 0 k h z 1 0 k h z c l k _ c l k s e l 1 [ 1 : 0 ] c l k _ c l k s e l 1 [ 1 : 0 ] h c l k h c l k 1 / 2 0 4 8 1 / ( u a r t d i v + 1 ) 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z p l l f o u t p l l f o u t 4 ~ 2 4 m h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z c l k _ c l k s e l 1 [ 2 5 : 2 4 ] 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z 1 0 k h z 1 0 k h z t 0 ~ t 3 t 0 ~ t 3 h c l k h c l k 4 ~ 2 4 m h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z c l k _ c l k s e l 2 [ 4 : 2 ] u s b 1 / ( u s b d i v + 1 ) p l l f o u t p l l f o u t s p i 1 p c l k p c l k 4 ~ 2 4 m h z 4 ~ 2 4 m h z 4 8 m h z 4 8 m h z p l l f o u t p l l f o u t c l k _ c l k s e l 2 [ 2 5 : 2 4 ] c l k _ c l k s e l 2 [ 2 7 : 2 6 ] 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z c l k _ c l k s e l 2 [ 1 8 ] a d c p c l k p c l k 4 ~ 2 4 m h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z p l l f o u t p l l f o u t c l k _ c l k s e l 1 [ 3 : 2 ] b o d 1 0 k h z 1 0 k h z 1 / ( a d c d i v ) + 1 c r c w w d t 1 0 k h z 1 0 k h z c l k _ c l k s e l 1 [ 3 1 : 3 0 ] c l k _ c l k s e l 1 [ 3 1 : 3 0 ] h c l k h c l k 1 / 2 0 4 8 s p i 0 c l o c k o u t p u t s m c 0 p c l k p c l k 4 ~ 2 4 m h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 2 2 . 1 1 8 4 m h z p l l f o u t p l l f o u t c l k _ c l k s e l 3 [ 1 : 0 ] c l k _ c l k s e l 3 [ 3 : 2 ] 4 8 m h z 4 8 m h z c l k _ c l k s e l 3 [ 8 ] a c m p i 2 c 0 p c l k 0 u s c i 0 / 2 4 8 m h z 4 8 m h z 4 8 m h z 4 8 m h z 4 8 m h z 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z e b i h d i v s m c 1 1 0 0 1 1 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 / 2 1 / 2 1 0 1 0 1 0 1 0 c l k _ c l k s e l 0 [ 7 ] c l k _ c l k s e l 0 [ 6 ] 0 1 1 0 1 1 0 0 1 0 0 1
nuc126 aug . 08 , 201 8 page 81 of 140 rev 1 .0 4 nuc126 series datasheet 6.3.2 system clock and systick clock the system clock has 6 clock sources, which were generated from clock generator block. the clock source switch depends on the register hclk sel (clk_clksel0 [2:0]). the block diagram is show n in figure 6.3 - 3 . note: before clock switching, both the pre - selected and newly selected clock source must be turned on and stable. figure 6.3 - 3 system clock block diagram there are two clock fail detectors to observe hxt and lxt clock source and they have individual enable and interrupt control. when hxt detector is enabled, the hirc clock is enabled automatically. when lxt detector is enabled, the lirc clock is enabled automatically. when hxt clock detector is enabled, the system clock will auto switch to hirc if hxt clock stop being detected on the following condition: system clock source comes from hxt or system clock source comes from pll with hxt as the input of pll. if hxt clock stop condition is detected, the hxtfif (clk_clkdsts[0]) is set to 1 and chip will enter interrupt if hxtfie n (clk_clkdctl[5]) is set to 1. user can trying to recover hxt by disable hxt and enable hxt again to check if the clock stable bit is set to 1 or not. if hxt clock stable bit is set to 1, it means hxt is recover to oscillate after re - enable action and user can switch system clock to hxt again. the hxt clock stop detect and system c lock switch to hirc procedure is shown in figure 6.3 - 4 . p l l f o u t l x t h x t l i r c h c l k s e l ( c l k _ c l k s e l 0 [ 2 : 0 ] ) h i r c 1 / ( h c l k _ n + 1 ) h c l k d i v ( c l k _ c l k d i v 0 [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k 1 / ( h c l k _ n + 1 ) 1 / ( h c l k d i v + 1 ) h i r c 4 8 1 / 2 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1
nuc126 aug . 08 , 201 8 page 82 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.3 - 4 hxt stop protect procedure the clock source of systick in cortex ? - m 0 core can use cpu clock or external clock (syst_ csr [2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the regi ster stclk sel (clk_clksel0[5:3]). the block diagram is show n in figure 6.3 - 5 . note: before clock switching, both the pre - selected and newly selected clock source must be turned on and stable. figure 6.3 - 5 systick clock control block diagram 6.3.3 peripherals clock the peripherals clock had different clock source switch setting, which depends on the different peripheral. please refer to the clk_clksel1 , clk_clksel2 and clk_clksel 3 register description in section 6 .3. 7 . s e t h x t f d e n t o e n a b l e h x t c l o c k d e t e c t o r h x t f i f = 1 ? s y s t e m c l o c k s o u r c e = h x t o r p l l w i t h h x t ? y e s s y s t e m c l o c k k e e p o r i g i n a l c l o c k n o y e s s w i t c h s y s t e m c l o c k t o h i r c n o 1 1 1 0 1 1 0 1 0 0 0 1 h x t l x t h x t h c l k s t c l k s e l ( c l k _ c l k s e l 0 [ 5 : 3 ] ) s t c l k h i r c 0 0 0 1 / 2 1 / 2 1 / 2
nuc126 aug . 08 , 201 8 page 83 of 140 rev 1 .0 4 nuc126 series datasheet 6.3.4 power - d own m ode clock when enter ing power - down mode, system clocks, some clock sources, and some peripheral clocks are disabled . some clock sources and peripherals clock are still active in power - down mode. for these s clocks, which still keep active, are list ed below: ? clock generator C 10 khz internal low - speed rc oscillator (lirc ) clock C 32.768 khz external low - speed crystal oscillator ( l xt ) clock ? peripherals clock (when the modules adopt lxt or lirc as clock source) 6.3.5 clock output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where f in is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in freqsel (clk_clkoctl[3:0]). when writ ing 1 to clkoen (clk_clkoctl[4]), the chained counter starts to count. when writ ing 0 to clkoen (clk_clkoctl[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. i f divi1 en ( clk_clkoctl [5]) set to 1, the clock output clock ( clko _clk) will bypass power - of - 2 frequency divider. the clock output clock will be output to c l ko pin directly. note: before clock switching, both the pre - selected and newly selected clock source must be turned on and stable. figure 6.3 - 6 clock source of clock output 0 1 1 0 1 0 0 0 1 0 0 0 h c l k l x t h x t h i r c c l k o s e l ( c l k _ c l k s e l 2 [ 4 : 2 ] ) c l k o c k e n ( c l k _ a p b c l k 0 [ 6 ] ) c l k o _ c l k 1 0 1 h i r c 4 8
nuc126 aug . 08 , 201 8 page 84 of 140 rev 1 .0 4 nuc126 series datasheet figure 6.3 - 7 clock output block diagram 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f r e q s e l ( c l k _ c l k o c t l [ 3 : 0 ] ) c l k o 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r c l k o e n ( c l k _ c l k o c t l [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r 0 1 d i v 1 e n ( c l k _ c l k o c t l [ 5 ] ) c l k o _ c l k 0 1 c l k 1 h z e n ( c l k _ c l k o c t l [ 6 ] ) 1 h z c l o c k f r o m r t c 0 1 l x t l i r c r t c s e l ( c l k _ c l k s e l 2 [ 1 8 ] ) / 3 2 7 6 8
nuc126 aug . 08 , 201 8 page 85 of 140 rev 1 .0 4 nuc126 series datasheet 6.4 flash memeory controller (fmc) 6.4.1 overview the nuc126 series is equipped with 128/256 kbytes on - chip embedded flash for application and configurable data flash to store some application dependent data. a user configuration block provides for system initiation. a 4 kbytes loader rom (ldrom) is used for in - system - programming (isp) function. a 2 kbytes security protection rom (sprom) can conceal user program. a 4kb cache with zer o wait cycle is used to improve flash access performance. this chip also supports in - application - programming (iap) function, user switches the code executing without the chip reset after the embedded flash updated. 6.4.2 features ? supports 128/ 2 56 kbytes a pplica tion rom (aprom) . ? supports 4 k bytes l oader rom (ldrom) . ? supports 2 kbytes security protection rom (sprom) to conceal user program. ? supports data f lash with configurable memory size. ? supports 12 bytes user configuration block to control system initiation. ? supports 2 kbytes page erase for all embedded flash. ? supports 32 - bit/64 - bit and multi - word flash programming function. ? supports crc - 32 checksum calculation function. ? supports flash all one verification function. ? supports embedded sram remap to system vect or memory. ? supports in - system - program ming (isp) / in - application - program ming (iap) to update embedded flash memory. ? supports cache memory to improve flash access performance and reduce power consumption.
nuc126 aug . 08 , 201 8 page 86 of 140 rev 1 .0 4 nuc126 series datasheet 6.5 analog comparator controller (acmp) 6.5.1 overview nuc12 6 contains two analog comparators. the comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0 . each comparator can be configured to generate an interrupt when the comparator output state changes. 6.5.2 features ? analog input voltage range: 0 ~ v dda ( voltage of av dd pin) ? supports hysteresis function ? supports wake - up function ? selectable input sources of positive input and negative input ? acmp0 supports C 4 positive sources : ? acmp0_p0, acmp0_p1, acmp0_p2, or acm p0_p3 C 3 negative sources : ? acmp0_n ? comparator reference voltage (crv) ? internal band - gap voltage ( v bg ) ? acmp1 supports C 4 positive sources : ? acmp1_p0, acmp1_p1, acmp1_p2, or acmp1_p3 C 3 negative sources ? acmp1_n ? comparator reference voltage (crv) ? internal band - gap voltage ( v bg ) ? share s one acmp interrupt vector for all comparators ? supports window latch mode ? supports window compare mode
nuc126 aug . 08 , 201 8 page 87 of 140 rev 1 .0 4 nuc126 series datasheet 6.6 analog - to - digital converter (ad c ) 6.6.1 overview the nuc126 series contains one 12 - bit successive approximation analog - to - digital converter (sar a/d converter) with twenty input channels. the a/d converter supports four operation modes: single, burst, single - cycle scan and continuous scan mode. the a/d converter c an be started by software, external pin (stadc/p d .2), timer0~3 overflow pulse trigger and pwm trigger. 6.6.2 features ? analog input voltage range: 0 ~ av dd . ? 12 - bit resolution and 10 - bit accuracy is guaranteed ? up to 20 single - end analog input channels or 10 diffe rential analog input channels ? maximum adc peripheral clock frequency is 16 mhz ? up to 800k sps sampling rate ? configurable adc internal sampling time ? four operation modes: C single mode: a/d conversion is performed one time on a specified channel. C burst mode: a/d converter samples and converts the specified single channel and sequentially stores the result in fifo. C single - cycle scan mode: a/d conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel. C continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion. ? an a/d conversion can be started by: C software write 1 to adst bit C external pin (stadc) C timer 0~3 overflow pulse trigger C pwm trigger with optional start delay period ? each conversion result is held in data register of each channel with valid and overrun indicators. ? conversion result can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting. ? 3 internal channels , t hey are band - gap voltage (v bg ), temperature sensor (v temp ), and battery power (v bat ) ? support pdma transfer mode. note1 : adc sampling rate = (adc peripheral clock f requency) / (total adc conversion cycle) note2 : if the internal channel (v temp ) is selected to convert, the sampling rate needs to be less than 300k sps for accurate result. note3 : if the internal channel for band - gap voltage is active, the maximum samplin g rate will be 300k sps .
nuc126 aug . 08 , 201 8 page 88 of 140 rev 1 .0 4 nuc126 series datasheet 6.7 crc controller (crc) 6.7.1 overview the cyclic redundancy check (crc) generator can perform crc calculation with four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 settings. 6.7.2 features ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 C crc - ccitt: x 16 + x 12 + x 5 + 1 C crc - 8: x 8 + x 2 + x + 1 C crc - 16: x 16 + x 15 + x 2 + 1 C crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? programmable seed value ? supports programmable order reverse setting for input data and crc checksum ? supports programmable 1s complement setting for input data and crc checksum ? supports 8/16/32 - bit of data width C 8 - bit write mode: 1 - ahb clock cycle operation C 16 - bit write mode: 2 - ahb clock cycle operation C 32 - bit write mode: 4 - ahb clock cycle operation ? supports using pdma to program data (crc_dat[31:0]) to perform crc operation
nuc126 aug . 08 , 201 8 page 89 of 140 rev 1 .0 4 nuc126 series datasheet 6.8 external bus interface (ebi) 6.8.1 overview the nuc126 series is equipped with an external bus interface (ebi) for external device used. to save the connections between external device and the nuc126 , ebi operating at address bus and data bus multiplex mode. the ebi supports two chip selects that can connect two external devices with different timing setting requirement. 6.8.2 features ? supports a ddress bus and data bus multiplex mode to save the address pins ? supports two chip selects with polarity control ? supports e xternal devices with maximum 1 m b size for each chip select ? supports v ariable external bus base clock (mclk) which based on hclk ? supp orts 8 - bit or 16 - bit data width for each chip select ? supports v ariable address latch enable time (tale ) ? supports v ariable data access time (tacc) and data access hold time (tahd) for each chip select ? supports c onfigurable idle cycle for different access condition: idle of write command finish (w2x) and idle of read - to - read (r2r) ? supports continuous data access mode to bypass tasu, tale and tlhd cycles for improving ebi access
nuc126 aug . 08 , 201 8 page 90 of 140 rev 1 .0 4 nuc126 series datasheet 6.9 g eneral purpose i/o (gpio) 6.9.1 overview the nuc126 series has up to 86 general purpose i/o pins to be shared with other function pins depending on the chip configuration. these 86 pins are arranged in 6 ports named as pa, pb, pc, pd, pe and pf. pa, pb, pc, pd has 1 6 pins on port. pe has 14 pins on port. pf has 8 pins on port. each of the 8 6 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as i nput, push - pull o utput, o pen - drain output or q uasi - bidirectional mode. after the chip is reset, the i/o mode of all pins are depending on cioin (config0[10]). each i/o pin has a very weakly individual pull - up resistor which is about 110 k ? ~ 300 k ? for v dd is from 5.0 v to 2.5 v. 6.9.2 features ? four i/o modes: C quasi - bidirectional mode C push - pull output mode C open - drain output mode C input only with high impendence mode ? ttl/schmitt trigger input selectable ? i/o pin can be configured as interrupt source with edge/level setting ? supports high slew rate i/o mode ? configurable default i/o mode of all pins after reset by cioini (config0[10]) setting C cioin = 0, all gpio pins in input tri - state mode after chip reset C cioin = 1, all gpio pins in quasi - bidirectional mode after chi p reset ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling the pin interrupt function will also enable the wake - up function
nuc126 aug . 08 , 201 8 page 91 of 140 rev 1 .0 4 nuc126 series datasheet 6.10 h ardware d ivider (hdiv) 6.10.1 overview the hardware divider (hdiv) is useful to the high performance application. the hardware divider is a signed, integer divider with both quotient and remainder outputs. 6.10.2 features ? signed (twos complement) integer calculation ? 32 - bit dividend with 16 - bit divisor calculation capacity ? 32 - bit quotient and 32 - bit remainder o utputs (16 - bit remainder with sign extends to 32 - bit) ? divided by zero warning flag ? 6 hclk clocks taken for one cycle calculation ? write divisor to trigger calculation ? waiting for calculation ready automatically when reading quotient and remainder 6.10.3 blcok d ia gram figure 6.10 - 1 hardware divider block diagram d i v i d e r c a l c u l a t i o n d i g i t a l c o n t r o l l o g i c d i v i d e n d s o u r c e r e g i s t e r ( d i v i d e n d ) d i v i s o r s o u r c e r e g i s t e r ( d i v i s o r ) q u o t i e n t r e s u l t r e g i s t e r ( d i v q u o ) s i g n e x t e n s i o n d i v i d e r s t a t u s r e g i s t e r ( d i v s t s ) r e m a i n d e r r e s u l t r e g i s t e r ( d i v r e m )
nuc126 aug . 08 , 201 8 page 92 of 140 rev 1 .0 4 nuc126 series datasheet 6.11 i 2 c serial interface controller (i 2 c) 6.11.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. there are two sets of i 2 c controller s which support power - down wake - up function. 6.11.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the i 2 c bus include: ? supports up to two i 2 c ports ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices wi th different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out co unter overflows ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four slave address with mask option) ? supports power - down wake - up function ? supports pdma with one buffer capability ? s upports two - level buffer function ? supports setup/hold time programmable
nuc126 aug . 08 , 201 8 page 93 of 140 rev 1 .0 4 nuc126 series datasheet 6.12 pdma controller (pdma) 6.12.1 overview the peripheral direct memory access (pdma) controller is used to provide high - speed data transfer. the pdma controller can transfer data from one address to another without cpu intervention. this has the benefit of reducing the workload of cpu and keeps cpu resources free for other applications. the pdma controller has a total of 5 channels and each channel can perform transfer between memory and pe ripherals or between memory and memory. the pdma supports time - out function for channel 0 and channel 1. 6.12.2 features ? supports 5 independently configurable channels ? supports selectable 2 level of priority (fixed priority or round - robin priority) ? supports transfer data width of 8, 16, and 32 bits ? supports source and destination address increment size can be byte, half - word, word or no increment ? supports software and spi, uart, i 2 s, i 2 c , usb, adc, pwm and timer request ? supports scatter - gather mode to perfor m sophisticated transfer through the use of the descriptor link list table ? supports single and burst transfer type ? supports time - out function for channel0 and channel 1
nuc126 aug . 08 , 201 8 page 94 of 140 rev 1 .0 4 nuc126 series datasheet 6.13 pwm generator and capture timer (pwm) 6.13.1 overview the nuc126 provides two pwm generator : pwm0 and pwm1 . e ach pwm supports 6 channels of pwm output or input capture. there is a 12 - bit prescaler to support flexible clock to the 16 - bit pwm counter with 16 - bit comparator. the pwm counter supports up, down and up - down counter types. pwm uses compa rator compared with counter to generate events. these events use to generate pwm pulse, interrupt and trigger signal for adc to start conversion . the pwm generator supports two standard pwm output modes: independent mode and complementary mode , they have d ifference architecture . there are two output functions based on standard output modes: group function and synchronous function . group function can be enable d under independent mode or complementary mode. synchronous function only enabled under complementar y mode. complementary mode has two comparators to generate various pwm pulse with 12 - bit d ead - time generator and another free trigger comparator to generate trigger signal for adc . for pwm output control unit, it supports polarity output, independent pin mask and brake functions . the pwm generator also supports input capture function. it supports latch pwm counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened. capture function also support pdma to transfer captured data to memory. 6.13.2 features 6.13.2.1 pwm function features ? supports maximum clock freque n cy up to144 mhz ? supports up to two pwm modules, each module provides 6 output channels. ? supports independent mode for pwm output/capture input channel ? supports complementary mode for 3 complementary paired pwm output channel s: C dead - time insertion with 12 - bit resolution C synchronous function for phase control C two compared values during one period ? supports 12 - bit pre - scal a r from 1 to 4096 ? supp orts 16 - bit resolution pwm counter C up, down and up - down counter operation type ? supports o ne - shot or a uto - reload counter operation mode ? supports group function ? supports synchronous function ? supports mask function and tri - state enable for each pwm output pin ? supports brake function C brake source from pin, analog comparator, adc result monitor and system safety events (clock failed, brown - out detection and cpu lockup). C noise filter for brake source from pin C leading edge blanking (leb) function for brake source from analog comparator C edge detect brake source to control brake state until brake interrupt cleared
nuc126 aug . 08 , 201 8 page 95 of 140 rev 1 .0 4 nuc126 series datasheet C level detect brake source to auto recover function after brake condition removed ? supports interrupt on the following events: C pwm zero point , period point , up - count compared or down - count compared point events C brake condition happened ? supports trigger adc on the following events: C pwm zero point , period point, zero or period point, up - count compared point, down - count compared point events C pwm up - count free trigger compared point, down - count free trigger compared point events 6.13.2.2 capture function features ? support s up to 6 c apture input channels with 16 - bit resolution for each pwm module ? supports r ising or falling capture condition ? supports input rising/fal ling capture interrupt ? supports rising/falling capture with counter reload option ? supports pdma transfer function for pwm all channels
nuc126 aug . 08 , 201 8 page 96 of 140 rev 1 .0 4 nuc126 series datasheet 6.14 real time clock (rtc) 6.14.1 overview the real time clock (rtc) controller provides the real time and calendar message. the rtc offers programmable time tick and alarm match interrupts. the data format of time and calendar messages are expressed in bcd f ormat. a digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. 6.14.2 fea tures ? supports real time counter in rtc_time (hour , minute , second) and calendar counter in rtc_cal (year , month , day) for rtc time and calendar check ? supports alarm time (hour , minute , second ) and calendar (year , month , day) settings in rtc_talm and rtc_c alm ? supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in rtc_tamsk and rtc_camsk ? selectable 12 - hour or 24 - hour time scale in rtc_clkfmt register ? ? supports leap y ear indication in rtc_leapyear register ? supports day of the w eek counter in rtc_weekday register ? frequency of rtc clock source compensate by rtc_freqadj register ? all time and calendar message expressed in bcd format ? support s periodic rtc t ime t ick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16 , 1/8, 1/4, 1/2 and 1 second ? support s rtc time tick and alarm match interrupt ? support s chip wake - up from idle or p ower - down mode while a n rtc interrupt signal is generated ? supports daylight saving time backup control in rtc _dstctl
nuc126 aug . 08 , 201 8 page 97 of 140 rev 1 .0 4 nuc126 series datasheet 6.15 smart card host interfa ce (sc) 6.15.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. 6.15.2 features ? iso - 7816 - 3 t = 0, t = 1 compliant ? emv2000 compliant ? two iso - 7816 - 3 port s ? separates receive/transmit 4 byte entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 267 etu) ? one 24 - bit timer and two 8 - bit timers for answer to request (atr) and waiting times processing ? supports auto direct / inverse convention function ? supports transmitter and receiver error retry and error number limiting function ? support s hardware activation sequence process , and the interval between pwr on and clk start is configurable ? support s hardware warm reset sequence process ? support s hardware deactivation sequence process ? supports hardware auto deactivation sequence when detected the card removal ? supports uart mode C full du plex, asynchronous communications C separates receiving/transmitting 4 bytes entry fifo for data payloads C supports programmable baud rate generator C supports programmable receiver buffer trigger level C programmable transmitting data delay time between the last stop bit leaving the tx - fifo and the de - assertion by setting egt (sc_egt[7:0]) C programmable even, odd or no parity bit generation and detection C programmable stop bit, 1 - or 2 - stop bit generation
nuc126 aug . 08 , 201 8 page 98 of 140 rev 1 .0 4 nuc126 series datasheet 6.16 serial peripheral interface (spi) 6.16.1 overview the serial peri pheral interface (spi) applies to synchronous serial data communication and allows full duplex transfer . devices communicate in m aster/ slave mode with the 4 - wire bi - direction interface. the nuc126 series contains up to two sets of spi controller s performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. each spi controller can be configured as a master or a slave device. this controller also supports the pdma function to access the data buffer . the spi controller also support i 2 s mode to connect external audio codec. 6.16.2 features ? spi mode C up to two sets of spi controller s C support s m aster or slave mode operation C configurable bit length of a trans action word from 8 to 32 - bit C provide s separate 4 - level depth transmit and receive fifo buffers C support s msb first or lsb first transfer sequence C support s b yte r eorder function C support s pdma transfer C supports one data channel half - duplex transfer C support receive - only mode ? i 2 s mode C supports m aster or s lave C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C provide s separate 4 - level depth transmit and receive fifo buffers C supports monaural and stereo audio data C supports pcm mode a, pcm mode b, i 2 s and ms b justified data format C support s pdma transfer
nuc126 aug . 08 , 201 8 page 99 of 140 rev 1 .0 4 nuc126 series datasheet 6.17 timer controller (tmr) 6.17.1 overview the timer c ontroller includes four 32 - bit timers, t imer 0 ~ t imer 3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. the timer controller also provides four pwm generators. each pwm generator supports two pwm output channels in independent mode and complementary mode . t h e output state of pwm output pin can be control by pin mask, polarity and break control, and dead - time generator. 6.17.2 features 6.17.2.1 timer f unction features ? four sets of 32 - bit timers , each timer equips one 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle - output and continuous counting operation modes ? 24 - bit up counter value is readable through cnt ( timerx_cnt[23:0] ) ? supports event counting fun ction ? 24 - bit capture value is readable through capdat ( timerx_cap[23:0] ) ? supports external capture pin event for interval measurement ? supports external capture pin event to reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated ? support timer0 ~ timer3 time - out interrupt signal or capture interrupt signal to trigger pwm, adc and pdma function ? supports internal capture triggered while internal acmp output signal transition ? supports inter - timer trigger mode ? supports event counting source from internal usb sof signal 6.17.2.2 pwm f unction f eatures ? supports maximum clock frequency up to 72mhz ? supports independent mode for pwm generator with two output channels ? supports complementary mode for pwm generator with pa ired pwm output channel C 12 - bit dead - time insertion with 12 - bit prescale ? supports 12 - bit prescale from 1 to 4096 ? supports 16 - bit pwm counter C up, down and up - down count operation type C one - shot or auto - reload counter operation mode ? supports mask function and tri - state enable for each pwm output pin
nuc126 aug . 08 , 201 8 page 100 of 140 rev 1 .0 4 nuc126 series datasheet ? supports brake function C brake source from pin, analog comparator and system safety events (clock failed, brown - out detection and cpu lockup) C brake pin noise filter control for brake source C edge detect brake source t o control brake state until brake interrupt cleared C level detect brake source to auto recover function after brake condition removed ? supports interrupt on the following events: C pwm zero point, period point, up - count compared or down - count compared point ev ents C brake condition happened ? supports trigger adc on the following events: C pwm zero point, period, zero or period point, up - count compared or down - count compared point events
nuc126 aug . 08 , 201 8 page 101 of 140 rev 1 .0 4 nuc126 series datasheet 6.18 usb device controller (usb d ) 6.18.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device. it is compliant with usb 2.0 full - speed device specification and supports control/bulk/interrupt/isochronous transfer types. it implements a full - speed (12 mbit/s) function interface with added support for usb 2.0 link power management. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. user needs to set the effective starting address of sram for each endpoint buffer through buffer segme ntation register (usbd_bufsegx). there are 8 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of e ndpoint c ontrol is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake - up idle event, device plug - in or plug - out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usbd_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usbd_epsts) to acknowledge what kind of event occurring in this endpoint. a software - disconnect function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables se0 bit (usbd_se0), the usb controller will force the output of usb_d+ and usb_d - to level low. it will casue host detect disconnect after user enab le se0 bit for a while. finally, user can disable the se0 bit, host will enumerate the usb device again. for more information on the universal serial bus, please refer to universal serial bus specification revision 1.1. 6.18.2 features ? compliant with usb 2.0 full - speed specification ? provide s 1 interrupt vector with 4 different interrupt events ( wkidle , vbusdet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type ? support s suspend function when no bus activity existing for 3 ms ? supports 8 endp oints for configurable control/bulk/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide s remote wake - up capability ? supports start of frame (sof) interrupt and usb frame number monitor. ? s upport s usb 2.0 l ink p ower management
nuc126 aug . 08 , 201 8 page 102 of 140 rev 1 .0 4 nuc126 series datasheet 6.19 usci C universal serial control interface controller 6.19.1 overview the universal serial control interface (usci) is a flexible interface module covering several serial communication protocols. the user can configure this controller as uart, spi, or i 2 c functional protocol. 6.19.2 features the controller can be individually confi gured to match the application needs. the following protocols are supported: ? uart ? spi ? i 2 c r x d p r x d m s 0 s 1 t r a n s c e i v e r u s b _ d + u s b _ d - s i e v b u s d e t e c t i o n d e - b o u n c i n g d p l l e n d p o i n t c o n t r o l b u f f e r c o n t r o l s r a m ( 5 1 2 b y t e s ) a p b b u s u s b c o n t r o l a n d s t a t u s r e g i s t e r s i n t e r r u p t c o n t r o l c l o c k g e n e r a t o r n v i c v b u s d e t e c t i o n u s b _ v b u s
nuc126 aug . 08 , 201 8 page 103 of 140 rev 1 .0 4 nuc126 series datasheet 6.20 usci C uart m ode 6.20.1 overview the asynchronous serial channel uart covers the reception and the transmission of asynchronous data frames. it performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the controller. the receiver and transmitter being independent, frames can start at different points in time for transmission and reception. the uart controller also provides auto flow control. there are two conditions to wake up the system. 6.20.2 features ? supports one transmit buffer and two receive buffer for data payload ? supports hardware auto flow control function ? supports programmable baud - rate generator ? support 9 - bit data transfer (support 9 - bit rs - 485) ? baud rate detection possible by built - in capture event of baud rate generator ? supports wake - up function (data and ncts wakeup only)
nuc126 aug . 08 , 201 8 page 104 of 140 rev 1 .0 4 nuc126 series datasheet 6.21 usci C spi m ode 6.21.1 overview the spi protocol of usci controller ap plies to synchronous serial data communication and allows full duplex transfer. it supports both master and slave operation mode with the 4 - wire bi - direction interface. spi mode of usci controller performs a serial - to - parallel conversion on data received f rom a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. the spi mode is selected by funmode (uspi_ctl[2:0]) = 0x 1. this spi protocol can operate as master or slave mode by setting the slave (uspi_protctl[0]) to communicate with the off - chip spi slave or master device. the application block diagrams in master and slave mode are shown below. figure 6.21 - 1 spi master mode application block diagram figure 6.21 - 2 spi slave mode application block diagram 6.21.2 features ? supports master or slave mode operation (the maximum frequency C master = f pclk / 2, slave < f pclk / 5) ? configurable bit length of a transfer word from 4 to 16 - bit ? supports one transmit buffer and two receive buffer s for data payload s p i s l a v e d e v i c e m a s t e r t r a n s m i t d a t a m a s t e r r e c e i v e d a t a s e r i a l b u s c l o c k s l a v e s e l e c t s p i _ m o s i ( u s c i x _ d a t 0 ) s p i _ m i s o ( u s c i x _ d a t 1 ) s p i _ c l k ( u s c i x _ c l k ) s p i _ s s ( u s c i x _ c t l ) s p i _ m o s i s p i _ m i s o u s c i s p i m a s t e r u s c i s p i m a s t e r s p i _ c l k s p i _ s s n o t e : x = 0 , 1 , 2 s p i m a s t e r d e v i c e s l a v e r e c e i v e d a t a s l a v e t r a n s m i t d a t a s e r i a l b u s c l o c k s l a v e s e l e c t s p i _ m o s i ( u s c i x _ d a t 0 ) s p i _ m i s o ( u s c i x _ d a t 1 ) s p i _ c l k ( u s c i x _ c l k ) s p i _ s s ( u s c i x _ c t l ) s p i _ m o s i s p i _ m i s o u s c i s p i s l a v e u s c i s p i s l a v e s p i _ c l k s p i _ s s n o t e : x = 0 , 1 , 2
nuc126 aug . 08 , 201 8 page 105 of 140 rev 1 .0 4 nuc126 series datasheet ? supports msb first or lsb first transfer sequence ? supports word suspend function ? supports 3 - wire, no slave select signal, bi - direction interface ? supports wake - up function by slave select signal in slave mode ? supports one data channel half - duplex transfer
nuc126 aug . 08 , 201 8 page 106 of 140 rev 1 .0 4 nuc126 series datasheet 6.22 usci C i 2 c m ode 6.22.1 overview on i 2 c bus, data is transferred between a master and a sl ave. data bits transfer on the scl and sda lines are synchronously on a byte - by - byte basis. each data byte is 8 - bit. there is one scl clock pulse for each data bit with the msb being transmitted first, and an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (s tart or stop). please refer to figure 6.22 - 1 for more detailed i 2 c bus timing. figure 6.22 - 1 i 2 c bus timing the devices on - chip i 2 c provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. the i 2 c mode is selected by funmode (ui2c_ctl [2:0]) = 100 b . when enable this port, the usci interfaces to the i 2 c bus via two pins: sda and scl . when i/o pins are used as i 2 c ports, user must set the pins function to i 2 c in advance. note: pull - up resistor is needed for i 2 c operation because the sda and scl are set to open - drain pins when usci is selected to i 2 c operation mode . 6.22.2 features ? full master and slave device capability ? support s of 7 - bit addressing, as well as 10 - bit addressing ? communication in standard mode (100 kbit/s) or in fast mode (up to 400 kbit/s) ? supports m ulti - master bus ? supports 10 - bit bus time - out capability ? supports bus moni tor mode. ? supports power down wake - up by data toggle or address match ? supports setup/hold time programmable ? supports multiple address recognition (two slave address with mask option) t b u f s t o p s d a s c l s t a r t t h d _ s t a t l o w t h d _ d a t t h i g h t f t s u _ d a t r e p e a t e d s t a r t t s u _ s t a t s u _ s t o s t o p t r
nuc126 aug . 08 , 201 8 page 107 of 140 rev 1 .0 4 nuc126 series datasheet 6.23 uart interface controller (uar t ) 6.23.1 overview the nuc126 series provides thr ee channels of universal asynchronous receiver/transmitters (uart). the uart controller performs normal speed uart and supports flow control function. the uart controller performs a serial - to - parallel conversion on data received from the peripheral and a p arallel - to - serial conversion on data transmitted from the cpu. each uart controller channel supports ten types of interrupts. the uart controller also supports irda sir, lin and rs - 485 function modes and auto - baud rate measuring function. 6.23.2 features ? full - dup lex asynchronous communications ? separate s receive and transmit 16/16 bytes entry fifo for data payloads ? supports hardware auto - flow control ? programmable receiver buffer trigger level ? supports programmable baud rate generator for each channel individually ? s upports n cts , incoming data, received data fifo reached threshold and rs - 485 address match (aad mode) wake - up function ? supports 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting dly (uart_tout [15:8]) ? supports auto - baud rate measurement and baud rate compensation function ? supports break error, frame error, parity error and receiv e/ transmit buffer overflow detect ion function ? fully programmable serial - interface characteristics C programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character C programmable parity bit, even, odd, no parity or stick parity bit generation and detection C programmable stop bit, 1, 1.5, or 2 stop bit generation ? supports irda sir function mode C support for 3/16 bit duration for normal mode ? supports lin function mode C supports lin master/slave mode C supports programmable break generation function for transmitter C supports break detection function for receiver ? supports rs - 485 function mode C supports rs - 485 9 - bit mode C supports hardware or software enables to program nrts pin to control rs - 485 transmission direction ? support pdma transfer function
nuc126 aug . 08 , 201 8 page 108 of 140 rev 1 .0 4 nuc126 series datasheet 6.24 watchdog timer (wdt) 6.24.1 overview the watchdog timer (wdt) is used to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, th e watchdog timer supports the function to wake up system from idle/power - down mode. 6.24.2 features ? supports 18 - bit free running up counter ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 1.6 ms ~ 26. 214 s if wdt_clk is 1 0 khz supports selectable wdt reset delay period between wdt time - out event to wdt reset system event , and it includ es 1026 130 18 or 3 * wdt_clk delay period ? system kept in re set state about 63 * wdt_clk period time after system reset event occurred ? supports to force wdt function enabled after chip powered on or reset by setting cwdten[2:0] in config0 register ? supports wdt time - out wake - up function only if wdt clock source is selected as lirc or lxt 6.24.3 clock control the wdt clock control is shown in figure 6.24 - 1 . figure 6.24 - 1 watchdog timer clock control 1 0 1 1 h c l k / 2 0 4 8 w d t s e l ( c l k _ c l k s e l 1 [ 1 : 0 ] ) w d t _ c l k 0 1 1 0 k h z ( l i r c ) 3 2 . 7 6 8 k h z ( l x t ) w d t c k e n ( c l k _ a p b c l k 0 [ 0 ] )
nuc126 aug . 08 , 201 8 page 109 of 140 rev 1 .0 4 nuc126 series datasheet 6.25 window watchdog timer (wwdt) 6.25.1 overview the window watchdog timer (wwdt) is used to perform a system reset while wwdt counter is n o t reload within a specified window period when application program run to uncontrollable status by any unpredictable condition. 6.25.2 features ? supports 6 - bit down counter value cntdat (wwdt_cnt[5:0]) and maximum 6 - bit compare value cmpdat (wwdt_ctl[21:16]) to a djust the wwdt compare time - out window period flexible ? supports pscsel (wwdt_ctl[11:8]) to programmable maximum 11 - bit prescale counter period of wwdt counter ? wwdt counter suspends in idle/power - down mode ? wwdt counter only can be reload ed within in valid window period to prevent system reset 6.25.3 clock control the wwdt clock control and block diagram are shown as follows. figure 6.25 - 1 wwdt clock control 1 1 h c l k / 2 0 4 8 w d t c k e n ( c l k _ a p b c l k 0 [ 0 ] ) w w d t _ c l k 1 0 1 0 k h z ( l i r c ) w w d t s e l ( c l k _ c l k s e l 2 [ 1 7 : 1 6 ] )
nuc126 aug . 08 , 201 8 page 110 of 140 rev 1 .0 4 nuc126 series datasheet 7 application circuit a v s s a v d d a v c c d v c c v s s v d d 0 . 1 u f f b f b p o w e r c r y s t a l n u c 1 2 6 s e r i e s c d e v i c e l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f u a r t r x d t x d d v c c s m a r t c a r d s l o t s c _ p w r s c _ r s t s c _ c l k s c _ d a t s c _ d e t e c t d v c c 1 0 u f / 1 0 v 1 0 k n r s t 4 ~ 2 4 m h z c r y s t a l 2 0 p 2 0 p x t 1 _ o u t x t 1 _ i n v d d v s s i 2 c l k d i o i 2 c _ s d a i 2 c _ s c l 4 . 7 k d v c c 4 . 7 k d v c c v d d i o v b a t v d d v s s n r e s e t i c e _ d a t i c e _ c l k s w d i n t e r f a c e v r e f 3 2 . 7 6 8 k h z c r y s t a l 2 0 p 2 0 p x 3 2 _ o u t x 3 2 _ i n l d o c a p _ 1 u f r e s e t c i r c u i t v d d v s s s p i d e v i c e c s c l k m i s o s p i _ s s m o s i s p i _ c l k s p i _ m i s o s p i _ m o s i d v c c u s b o t g s l o t u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ v b u s 1 u f 3 3 r 3 3 r
nuc126 aug . 08 , 201 8 page 111 of 140 rev 1 .0 4 nuc126 series datasheet 8 electrical character istics 8.1 absolute maximum ratings symbol parameter min max unit dc power supply v dd - v ss - 0.3 +7.0 v input voltage v in v ss C 0.3 v dd + 0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 +1 0 5 ? c storage temperature t st - 55 +150 ? c maximum current into v dd i dd - 120 ma maximum current out of v ss i ss - 120 ma maximum current sunk by a i/o pin i io - 35 ma maximum current sourced by a i/o pin - 35 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of th e device.
nuc126 aug . 08 , 201 8 page 112 of 140 rev 1 .0 4 nuc126 series datasheet 8.2 dc electrical characteristics (v dd - v ss = 2.5 ~ 5.5v, ta = 25 ? c , f osc = 72 mhz unless otherwise specified.) parameter sym. specifications test conditions min. typ. max. unit operation v oltage v dd C v ss 2.5 - 5.5 v v dd = 2.5 ~ 5.5 v up to 72 mhz power supply for p e . 8 ~ p e . 13 v ddio C v ss 1.8 - 5.5 v power supply for pf.0, pf.1 and pf.2 v bat C v ss 2.5 - 5.5 v power ground v ss C av ss - 0.05 - +0.05 v ldo output voltage v ldo 1.62 1.8 1.98 v mcu operating in run , idle or power - down mode c ldo 1 uf connect to ldo_cap pin band - gap voltage v bg - 1.21 - v allowed voltage difference for v dd and av dd v dd C a v dd - 0.3 - +0.3 v operating current normal run mode hclk = 72 mhz while(1){}executed from flash v ldo =1.8 v i dd 1 - 57 - ma v dd hxt hirc hirc48 pll all digital module 5.5 v 12 mhz x x v v i dd 2 - 22 - ma 5.5 v 12 mhz x x v x i dd 3 - 57 - ma 3.3 v 12 mhz x x v v i dd 4 - 22 - ma 3.3 v 12 mhz x x v x operating current normal run mode hclk = 72 mhz while(1){}executed from flash v ldo =1.8 v i dd 5 - 5 5 - ma v dd hxt hirc hirc48 pll all digital module 5.5 v x x v v v i dd 6 - 2 1 - ma 5.5 v x x v v x i dd 7 - 55 - ma 3.3 v x x v v v i dd 8 - 21 - ma 3.3 v x x v v x operating current normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i dd 9 - 3 3 - ma v dd hxt hirc hirc48 pll all digital module 5.5 v 12 mhz x x v v i dd 10 - 1 4 - ma 5.5 v 12 mhz x x v x i dd 11 - 33 - ma 3.3 v 12 mhz x x v v i dd 12 - 1 4 - ma 3.3 v 12 mhz x x v x
nuc126 aug . 08 , 201 8 page 113 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit operating current normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i dd 13 - tbd - ma v dd hxt hirc hirc48 pll all digital module 5.5 v x x v x v i dd 14 - tbd - ma 5.5 v x x v x x i dd 15 - tbd - ma 3.3 v x x v x v i dd 16 - tbd - ma 3.3 v x x v x x operating current normal run mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i dd 17 - 15.8 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 24 mhz x x x v i dd 18 - 6. 7 - ma 5.5 v 24 mhz x x x x i dd 19 - 15.8 - ma 3.3 v 24 mhz x x x v i dd 20 - 6. 7 - ma 3.3 v 24 mhz x x x x operating current normal run mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i dd 21 - tbd - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x x hirc 48/2 x v i dd 22 - tbd - ma 5.5 v x x hirc 48/2 x x i dd 23 - tbd - ma 3.3 v x x hirc 48/2 x v i dd 24 - tbd - ma 3.3 v x x hirc 48/2 x x operating current normal run mode hclk = 22.1184 mhz while(1){}executed from flash v ldo =1.8 v i dd 25 - 16.6 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x v x x v i dd 26 - 6. 2 - ma 5.5 v x v x x x i dd 27 - 16. 6 - ma 3.3 v x v x x v i dd 28 - 6. 2 - ma 3.3 v x v x x x operating current normal run mode hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v i dd 29 - 7. 8 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 12 mhz x x x v i dd 30 - 3. 1 - ma 5.5 v 12 mhz x x x x i dd 3 1 - 7. 8 - ma 3.3 v 12 mhz x x x v i dd 32 - 3.1 - ma 3.3 v 12 mhz x x x x operating current normal run mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i dd 33 - 2.74 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 4 mhz x x x v i dd 34 - 1.23 - ma 5.5 v 4 mhz x x x x i dd 35 - 2.72 - ma 3.3 v 4 mhz x x x v i dd 36 - 1.20 - ma 3.3 v 4 mhz x x x x operating current i dd 37 - 13 6 - u a v dd lxt lirc pll all digital module
nuc126 aug . 08 , 201 8 page 114 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit normal run mode hclk = 32.768 k hz while(1){}executed from flash v ldo =1.8 v 5.5 v 32.768 khz x x v i dd 38 - 12 3 - u a 5.5 v 32.768 khz x x x i dd 39 - 123 - u a 3.3 v 32.768 khz x x v i dd 40 - 10 9 - u a 3.3 v 32.768 khz x x x operating current normal run mode hclk = 10 k hz while(1){}executed from flash v ldo =1.8 v i dd 41 - 12 1 - u a v dd lxt lirc pll all digital module 5.5 v x 10 khz x v i dd 42 - 11 7 - u a 5.5 v x 10 khz x x i dd 43 - 10 7 - u a 3.3 v x 10 khz x v i dd 44 - 10 2 - u a 3.3 v x 10 khz x x operating current idle mode hclk = 72 mhz while(1){}executed from flash v ldo =1.8 v i idle 1 - 4 7 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 12 mhz x x v v i idle2 - 9 - ma 5.5 v 12 mhz x x v x i idle3 - 4 7 - ma 3.3 v 12 mhz x x v v i idle4 - 9 - ma 3.3 v 12 mhz x x v x operating current idle mode hclk = 72 mhz while(1){}executed from flash v ldo =1.8 v i idle5 - 4 7 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x x v v v i idle6 - 9 .5 - ma 5.5 v x x v v x i idle7 - 4 7 - ma 3.3 v x x v v v i idle8 - 9. 5 - ma 3.3 v x x v v x operating current idle mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i idle9 - 2 7 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 12 mhz x x v v i idle10 - 5. 5 - ma 5.5 v 12 mhz x x v x i idle11 - 27 - ma 3.3 v 12 mhz x x v v i idle12 - 5. 5 - ma 3.3 v 12 mhz x x v x operating current idle mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i idle13 - tbd - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x x v x v i idle14 - tbd - ma 5.5 v x x v x x i idle15 - tbd - ma 3.3 v x x v x v i idle16 - tbd - ma 3.3 v x x v x x operating current idle mode hclk = 24 mhz i idle17 - 12. 5 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 24 mhz x x x v
nuc126 aug . 08 , 201 8 page 115 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit while(1){}executed from flash v ldo =1.8 v i idle18 - 2.2 - ma 5.5 v 24 mhz x x x x i idle19 - 12. 5 - ma 3.3 v 24 mhz x x x v i idle20 - 2. 2 - ma 3.3 v 24 mhz x x x x operating current idle mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i idle21 - tbd - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x x hirc 48/2 x v i idle22 - tbd - ma 5.5 v x x hirc 48/2 x x i idle23 - tbd - ma 3.3 v x x hirc 48/2 x v i idle24 - tbd - ma 3.3 v x x hirc 48/2 x x operating current idle mode hclk = 22.1184 mhz while(1){}executed from flash v ldo =1.8 v i idle25 - 12. 3 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v x v x x v i idle26 - 1.9 - ma 5.5 v x v x x x i idle27 - 12. 3 - ma 3.3 v x v x x v i idle28 - 1. 9 - ma 3.3 v x v x x x operating current idle mode hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v i idle 29 - 6.3 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 12 mhz x x x v i idle 30 - 1. 2 - ma 5.5 v 12 mhz x x x x i idle 31 - 6. 3 - ma 3.3 v 12 mhz x x x v i idle 32 - 1. 2 - ma 3.3 v 12 mhz x x x x operating current idle mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i idle 33 - 2. 2 - ma v dd hxt hirc hirc 48 pll all digital module 5.5 v 4 mhz x x x v i idle 34 - 0.50 - ma 5.5 v 4 mhz x x x x i idle 35 - 2. 2 - ma 3.3 v 4 mhz x x x v i idle 36 - 0.46 - ma 3.3 v 4 mhz x x x x operating current idle mode hclk = 32.768 k hz while(1){}executed from flash v ldo =1.8 v i idle 37 - 129 - u a v dd lxt lirc pll all digital module 5.5 v 32.768 khz x x v i idle 38 - 115 - u a 5.5 v 32.768 khz x x x i idle 39 - 115 - u a 3.3 v 32.768 khz x x v i idle 40 - 101 - u a 3.3 v 32.768 khz x x x operating current idle mode hclk = 10 k hz while(1){}executed from flash i idle 41 - 119 - u a v dd lxt lirc pll all digital module 5.5 v x 10 khz x v i idle 42 - 114 - u a 5.5 v x 10 khz x x
nuc126 aug . 08 , 201 8 page 116 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit v ldo =1.8 v i idle 43 - 104 - u a 3.3 v x 10 khz x v i idle 44 - 100 - u a 3.3 v x 10 khz x x standby current power - down mode v ldo =1.8 v i pwd1 - tbd - u a v dd hxt/hirc lxt /lirc pll ram retention 5.5 v x lxt x v i pwd2 - tbd - u a 5.5 v x lirc x v i pwd3 - tbd - u a 5.5 v x lxt & lirc x v i pwd4 - 20 u a 5.5 v x x x v i pwd5 - 1 3.5 - u a 3.3 v x lxt x v i pwd6 - 1 3 .3 - u a 3.3 v x lirc x v i pwd7 - 1 4 .3 - u a 3.3 v x lxt & lirc x v i pwd8 - 1 2.5 - u a 3.3 v x x x v logic 0 input current (quasi - bidirectional mode) i il - - 70 - ua v dd = v bat = v ddio = 5.5v , v in = 0v logic 1 to 0 transition current (quasi - bidirectional mode) [3] i tl - - 620 - ua v dd = v bat = v ddio = 5.5v , v in = 2.0v input pull up resistor r in - tb d - k v dd = v bat = v ddio = 5 . 5 v - tb d - k v dd = v bat = v ddio = 3.3v - tb d - k v dd = v bat = 2.5 ~ 5.5 v v ddio = 1.8 v input leakage current i lk - 0 - ? a v dd = v bat = v ddio = 5.5v, 0 < v in < v dd open - drain or input only mode input low voltage (ttl input) v il1 - 0.3 - 0.8 v v dd = v bat = v ddio = 4.5 v - 0.3 - 0.6 v v dd = v bat = v ddio = 2 .5 v input low voltage (ttl input for v ddio domain ) v il2 - 0.3 - tb d v v dd = v bat = 2.5 ~ 5.5 v v ddio = 1.8 v input high voltage (ttl input) v ih1 2.0 - v dd + 0.3 v v dd = v bat = v ddio = 5 .5v 1.5 - v dd + 0.3 v v dd = v bat = v ddio = 2 .5v input high voltage (ttl input for v ddio domain ) v ih2 tb d - v dd + 0.3 v v dd = v bat = 2.5 ~ 5.5 v v ddio = 1.8 v input low voltage (schmitt input) v il3 - 0.3 - 0.3v dd v v dd = v bat = v ddio = 2.5 ~ 5.5 v
nuc126 aug . 08 , 201 8 page 117 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit input low voltage (schmitt input for v ddio domain ) v il4 - 0.3 - 0.3v dd v v ddio = 1.8 ~ 5.5v input high voltage (schmitt input) v ih3 0.7v dd - v dd + 0.3 v v dd = v bat = v ddio = 2.5 ~ 5.5v input high voltage (schmitt input for v ddio domain ) v ih4 0.7v ddi o - v ddio + 0.3 v v ddio = 1.8 ~ 5.5v hysteresis voltage of pa~pf (schmitt input) v hy - 0.2v dd - v negative going threshold (schmitt input), n reset v il 5 - 0.3 - 0.2v dd v positive going threshold (schmitt i n put), n reset v ih 5 0.8v dd - v dd + 0.3 v internal nreset pin pull up resistor r rst - 16 - k v dd = 5 . 5 v source current (quasi - bidirectional mode) i sr1 - - 4 00 - ua v dd = v bat = v ddio = 4.5v, v s = 2.4v i sr2 - - 8 0 - ua v dd = v bat = v ddio = 2.7v, v s = 2.2v i sr3 - - 7 3 - ua v dd = v bat = v ddio = 2.5v, v s = 2.0v source current (quasi - bidirectional mode for v ddio domain ) i sr 4 - - 19 - ua v dd = v bat = 2.5 ~ 5.5v v ddio = 1.8v, v s = 1.6v source current (push - pull mode) i sr 5 - 18 - 26 ma v dd = v bat = v ddio = 4.5v, v s = 2.4v i sr6 - - 5.8 - ma v dd = v bat = v ddio = 2.7v, v s = 2.2v i sr 7 - - 5.2 - ma v dd = v bat = v ddio = 2.5v, v s = 2.0v source current (push - pull mode for v ddio domain ) i s r8 - - 1.5 - ma v dd = v bat = 2.5 ~ 5.5v v ddio = 1.8v, v s = 1.6v sink current (quasi - bidirectional, open - drain and push - pull mode) i sk1 7 1 5 - ma v dd = v bat = v ddio = 4.5v, v s = 0.45v i sk2 - 10 - ma v dd = v bat = v ddio = 2.7v, v s = 0.45v i sk3 - 9 - ma v dd = v bat = v ddio = 2.5v, v s = 0.45v
nuc126 aug . 08 , 201 8 page 118 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit sink current (quasi - bidirectional, open - drain and push - pull mode for v ddio domain ) i sk4 - - 2.2 - ma v dd = v bat = 2.5 ~ 5.5v v ddio = 1.8v, v s = 1.6v higher gpio rising rate hiorr 1 - 2.46 - ns v dd = v bat = v ddio = 5.5v , without capacitor hiorr 2 3.24 ns v dd = v bat = v ddio = 5.5v , with 10pf capacitor hiorr 3 - 3.12 - ns v dd = v bat = v ddio = 3.0 v , without capacitor hiorr 4 - 4.56 - ns v dd = v bat = v ddio = 3.0 v , with 10pf capacitor hiorr 5 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , without capacitor (for vddio domain) hiorr 6 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , with 10pf capacitor (for vddio domain) basic gpio rising rate biorr 1 - 3.24 - ns v dd = v bat = v ddio = 5.5v , without capacitor biorr 2 - 4.15 - ns v dd = v bat = v ddio = 5.5v , with 10pf capacitor biorr 3 - 4. 75 - ns v dd = v bat = v ddio = 3.0 v , without capacitor biorr 4 - 6.43 - ns v dd = v bat = v ddio = 3.0 v , with 10pf capacitor biorr 5 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , without capacitor (for vddio domain) biorr 6 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , with 10pf capacitor (for vddio domain) higher gpio falling rate hiofr 1 - 2.10 - ns v dd = v bat = v ddio = 5.5v , without capacitor
nuc126 aug . 08 , 201 8 page 119 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test conditions min. typ. max. unit hiofr 2 - 2. 83 - ns v dd = v bat = v ddio = 5.5v , with 10pf capacitor hiofr 3 - 3.12 - ns v dd = v bat = v ddio = 3.3 v , without capacitor hiofr 4 - 4.19 - ns v dd = v bat = v ddio = 3.3 v , with 10pf capacitor hiofr 5 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , without capacitor ( for v ddio domain ) hiofr 6 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , with 10pf capacitor ( for v ddio domain ) basic gpio falling rate biofr 1 - 3.42 - ns v dd = v bat = v ddio = 5.5v , without capacitor biofr 2 - 4 .4 0 - ns v dd = v bat = v ddio = 5.5v , with 10pf capacitor biofr 3 - 6.14 - ns v dd = v bat = v ddio = 3.3 v , without capacitor biofr 4 - 7.87 - ns v dd = v bat = v ddio = 3.3 v , with 10pf capacitor biofr 5 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , without capacitor ( for v ddio domain ) biofr 6 - tb d - ns v dd = v bat = 2.5 ~ 5.5v , v ddio = 1.8 v , with 10pf capacitor ( for v ddio domain )
nuc126 aug . 08 , 201 8 page 120 of 140 rev 1 .0 4 nuc126 series datasheet 8.3 ac electrical characteristics 8.3.1 external 4~24 mhz high speed crystal (hxt) input clock parameter sym. specifications test condition min. typ. max. unit clock high time t chcx 10 - - ns clock low time t clcx 10 - - ns clock rise time t clch 2 - 15 ns clock fall time t chcl 2 - 15 ns input high voltage v ih 0.7v dd - v dd v input low voltage v il 0 - 0.3v dd v note: duty cycle is 50%. 8.3.2 external 4~2 4 mhz high speed crystal (hxt) oscillator parameter sym. specifications test condition min. typ. max. unit oscillator frequency f hxt 4 - 24 mhz v dd = 2 . 5 ~ 5 . 5 v temperature t hxt - 40 - +105 ? c operating current i hxt - tb d - m a v dd = 5.5 v @ 12mhz - 0. 4 - m a v dd = 3. 3 v @ 12mhz 8.3.2.1 typical crystal application circuits crystal c1 c2 r 1 4mhz ~ 24 mhz 20pf 20pf without t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l v i l v i h
nuc126 aug . 08 , 201 8 page 121 of 140 rev 1 .0 4 nuc126 series datasheet figure 8.3 - 1 typical crystal application circuit 8.3.3 external 32.768 khz low speed crystal (lxt) input clock parameter sym. specifications test condition min. typ. max. unit clock high time t chcx tbd - - ns clock low time t clcx tbd - - ns clock rise time t clch tbd - tbd ns clock fall time t chcl tbd - tbd ns lxt input pin input high voltage xin_v ih 0.7 v l d o - v l d o v lxt input pin input low voltage xin_v il 0 - 0.3v l d o v note: duty cycle is 50%. x t _ i n x t _ o u t c 1 r 1 c 2 t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l x i n _ v i l x i n _ v i h
nuc126 aug . 08 , 201 8 page 122 of 140 rev 1 .0 4 nuc126 series datasheet 8.3.4 external 32.768 khz low speed crystal (lxt) input clock parameter sym. specifications test condition min. typ. max. unit oscillator frequency f lxt - 32.768 - khz v dd = v bat = 2.5 ~ 5 . 5 v temperature t lxt - 40 - +105 ? c operating current i lxt 0.7 ? a v dd = v bat = 2.5 ~ 5 . 5 v 8.3.4.1 typical crystal application circuits crystal c 3 c 4 r 2 32.768 khz 20pf 20pf without figure 8.3 - 2 typical crystal application circuit x t _ i n x t _ o u t c 3 r 2 c 4
nuc126 aug . 08 , 201 8 page 123 of 140 rev 1 .0 4 nuc126 series datasheet 8.3.5 internal 48 mhz high speed rc oscillator (hirc 48 ) parameter sym. specifications test condition min. typ. max. unit center frequency f hrc - 48 - mhz t a = 25 ? c , v dd = 3 .3 v calibrated internal oscillator frequency - 1 - +1 % t a = 25 ? c , v dd = 2.5 ~ 5.5 v - 2 - +2 % t a = - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v - 0.25 - +0.25 % t a = - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v auto trimmed by lxt operating current i hrc - 4 40 - ? a 8.3.6 internal 22.1184 mhz high speed rc oscillator (hirc) parameter sym. specifications test condition min. typ. max. unit center frequency f hrc - 22.11 84 - mhz t a = 25 ? c , v dd = 3 .3 v calibrated internal oscillator frequency - 1 - +1 % t a = 25 ? c , v dd = 2.5 ~ 5.5 v - 2 - +2 % - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v - 0.25 - +0.25 % - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v auto trimmed by lxt operating current i hrc - 4 70 - ? a 8.3.7 internal 10 khz low speed rc oscillator (lirc) parameter sym. specifications test condition min. typ. max. unit center frequency f lrc - 10 - khz t a = 25 ? c , vdd = 3 .3 v calibrated internal oscillator frequency - 30 - +30 % t a = 25 ? c , vdd = 2.5 ~ 5.5 v
nuc126 aug . 08 , 201 8 page 124 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test condition min. typ. max. unit - 50 - +50 % - 40 ? c ~+ 105 ? c , vdd = 2.5 ~ 5.5 v operating current i lrc 0.9 ? a
nuc126 aug . 08 , 201 8 page 125 of 140 rev 1 .0 4 nuc126 series datasheet 8.4 analog characteristics 8.4.1 ldo parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c dc power supply v dd 2.5 - 5.5 v output voltage v ldo 1.62 1.8 1.98 v note 1 : it is recommended a 0.1f bypass capacitor is connected between v dd and the closest v ss pin of the device. note 2 : for ensuring power stability, a 1f capacitor must be connected between ldo_cap pin and the closest v ss pin of the device. 8.4.2 temperature sensor parameter sym. specifications test condition min. typ. max. unit detection temperature t det - 40 - + 105 o c gain v tg - 1.76 - 1. 70 - 1.64 mv/ o c offset v to - 7 45 - mv temperature at 0 o c operating current i temp 6.4 - 10.5 ? a note 1 : the temperature sensor formula for the output voltage (vtemp) is as below equation. vtemp (mv) = gain (mv/ ) x temperature ( ) + offset (mv) 8.4.3 internal voltage reference ( int_v ref ) parameter sym. specifications test condition min. typ. max. unit v ref (2.048v) v ref1 1.986 - 2. 151 v vrefctl = 3, av dd 2. 5 v v ref ( 2.56v ) v ref2 2.483 - 2.637 v vrefctl = 3, av dd 2. 9 v v ref ( 3.072v ) v ref3 2.98 - 3.164 v vrefctl = 3, av dd 3 .4v v ref ( 4.096v ) v ref4 3.973 - 4.219 v vrefctl = 3, av dd 4 . 5 v start - up time t vref _start - 700 2000 us c vref = 4.7uf operating current i vref 100 ? a
nuc126 aug . 08 , 201 8 page 126 of 140 rev 1 .0 4 nuc126 series datasheet 8.4.4 power - on reset parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c threshold voltage v por - 2 - v 8.4.5 low - voltage reset parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c threshold voltage v lv r 2.0 2. 2 2.4 5 v t a = +105 1.8 2.0 2.2 v t a = +25 1.7 5 1.9 5 2. 2 v t a = - 40 start - up time t lvr_start - 130 - us t a = +25 quiescent current i lvr - 1.1 - ua av dd = 5.5v 8.4.6 brown - out detector parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c brown - out voltage (falling edge) v bod f 4. 2 4.4 4. 6 v bodvl [1:0] = 11 3. 5 3.7 3. 9 v bodvl [1:0] = 1 0 2. 55 2.7 2. 8 5 v bodvl [1:0] = 0 1 2. 05 2.2 2. 3 5 v bodvl [1:0] = 00 brown - out voltage ( rising edge) v bod r 4. 3 4.5 4. 7 v bodvl [1:0] = 11 3. 6 3.8 4 . 0 v bodvl [1:0] = 1 0 2. 6 2. 75 2.9 v bodvl [1:0] = 0 1 2. 1 2. 25 2.4 v bodvl [1:0] = 00 start - up time t bod_start - 1030 - us t a = +25 quiescent current i bod 83 - ua t a = +25 , av dd = 5.5v bodlpm = 0
nuc126 aug . 08 , 201 8 page 127 of 140 rev 1 .0 4 nuc126 series datasheet parameter sym. specifications test condition min. typ. max. unit 0.7 ua t a = +25 , av dd = 5.5v bodlpm = 1 8.4.7 12 - bit adc parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c operating voltage av dd 3.0 - 5.5 v av dd = v dd reference voltage v ref 3 .0 av dd v adc input voltage v in 0 - av ref v resolution r adc 12 bit integral non - linearity error inl - 2 +1.5 +2 lsb differential non - linearity dnl - 1 +1.5 +2 lsb gain error e g - 4 - 2 +4 lsb offset error e offset - 4 2 +4 lsb absolute error e abs - 4 - +4 lsb monotonic - guaranteed - adc clock frequency f adc 1 16 mhz acquisition time (sample stage) t acq 2 7 21 1/f adc default: 7 (1/fadc) conversion time t conv 15 20 34 1/f adc t conv = t acq + 13 default: 20 (1/fadc) conversion rate (f adc /t conv ) f sps - - 800 ksps t conv = 20 clock f adc = 16 m h z internal capacitance [ 1 ] c in - tb d - pf input load [1] r in - tb d - k operating current i adc 1 - 4 - m a av dd = v dd = 5 v adc clock rate = 16 mhz note 1 : design by guarantee, no test in production.
nuc126 aug . 08 , 201 8 page 128 of 140 rev 1 .0 4 nuc126 series datasheet note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. typical connection diagram using the adc note: gnd < ain x < v ref < vdd 1 2 3 4 5 6 4 0 9 5 4 0 9 4 7 4 0 9 3 4 0 9 2 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 4 0 9 5 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b v d d 1 2 - b i t c o n v e r t e r a i n x r i n c i n ( 1 ) ( 1 )
nuc126 aug . 08 , 201 8 page 129 of 140 rev 1 .0 4 nuc126 series datasheet 8.4.8 analog comparator parameter sym. specifications test condition min. typ. max. unit temperature t a - 40 - + 105 o c input common mode range v com 0.1 - av dd - 0.1 v input offset voltage v off - 10 - mv hysen = 0 hysteresis v hys 10 6 0 - mv hysen = 1, v cm = av dd /2 dc gain [1 005d - 40 70 db propagation delay t pgd 125 200 ns v cm = 1.2 v, v diff = 0.1 v stable time t stb 0.35 1 us av dd = 5v operation current i cmp 35 70 ua reference voltage v ref 3 .0 av dd v adc input voltage v in 0 - av ref v note 1 : guaranteed by design, not tested in production.
nuc126 aug . 08 , 201 8 page 130 of 140 rev 1 .0 4 nuc126 series datasheet 8.4.9 usb phy 8.4.9.1 low - full - speed dc electrical specifications symbol parameter min. typ. max. unit test conditions v ih input h igh (driven) 2.0 - - v - v il input l ow - - 0.8 v - v di differential i nput s ensitivity 0.2 - - v |padp - padm| v cm differential c ommon - mode r ange 0.8 - 2.5 v includes v di range v se single - ended r eceiver t hreshold 0.8 - 2.0 v - receiver h ysteresis - 200 - mv - v ol output l ow (driven) 0 - 0.3 v - v oh output h igh (driven) 2.8 - 3.6 v - v crs output s ignal c ross v oltage 1.3 - 2.0 v - r pu pull - up r esistor 1.425 - 1.575 k - r pd pull - down resistor 14.25 - 15.75 k v trm termination voltage for uptream port pull up (rpu) 3.0 - 3.6 v z drv driver o utput r esistance - 10 - steady state drive* c in transceiver c apacitance - - 20 pf pin to gnd *driver output resistance doesnt include series resistor resistance. 8.4.9.2 usb full - speed driver electrical characteristics symbol parameter min. typ. max. unit test conditions t fr rise time 4 - 20 ns c l =50p t ff fall time 4 - 20 ns c l =50p t frff rise and f all t ime m atching 90 - 111.11 % t frff =t fr /t ff 8.4.9.3 usb ldo specification symbol parameter min. typ. max. unit test conditions v bus v bus pin input voltage 4.0 5.0 5.5 v - v dd33 ldo output voltage 3.0 3.3 3.6 v - c bp external bypass capacitor - 1.0 - uf -
nuc126 aug . 08 , 201 8 page 131 of 140 rev 1 .0 4 nuc126 series datasheet 8.5 flash dc electrical characteris symbol parameter min typ max unit test condition v fla [1] supply voltage 1.62 1.8 1.98 v t a = 25 n endur endurance 20,000 - - cycles [2] t ret data retention 100 - - year t erase page erase time 20 - 40 ms t m e r mass erase time 20 - 40 ms t prog program time 20 - 40 us i dd1 read current - - tbd ma i dd2 program current - - tbd ma i dd3 erase current - - tbd ua note 1: v fla is source from chip ldo output voltage. note 2: number of program/erase cycles. note 3: this table is guaranteed by design, not test in production.
nuc126 aug . 08 , 201 8 page 132 of 140 rev 1 .0 4 nuc126 series datasheet 8.6 i2c dynamic characteristics symbol parameter standard m ode [1][2] fast m ode [1][2] unit min . max . min . max . t low scl low period 4.7 - 1.2 - us t high scl high period 4 - 0.6 - us t su; sta repeated start condition setup time 4.7 - 1.2 - us t hd; sta start condition hold time 4 - 0.6 - us t su; sto stop condition setup time 4 - 0.6 - us t buf bus free time 4.7 [3] - 1.2 [3] - us t su;dat data setup time 250 - 100 - ns t hd;dat data hold time 0 [4] 3.45 [5] 0 [4] 0.8 [5] us t r scl/sda rise time - 1000 20+0.1cb 300 ns t f scl/sda fall time - 300 - 300 ns c b capacitive load for each bus line - 400 - 400 pf notes : 1. guaranteed by design, not tested in production. 2. hclk must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 8 mhz to achieve the maximum fast mode i 2 c frequency. 3. i 2 c controller must be retriggered immediately at slave mode after receiving stop condition. 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of th e falling edge of scl. 5. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. figure 8.6 - 1 i 2 c timing diagram t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
nuc126 aug . 08 , 201 8 page 133 of 140 rev 1 .0 4 nuc126 series datasheet 8.7 spi dynamic characteristics 8.7.1 dynamic characteristics of data input and output pin symbol parameter min . typ . max . unit spi m aster m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t ds data setup time 4 2 - ns t dh data hold time 0 - - ns t v data output valid time - 7 11 ns spi m aster m ode (vdd = 3 . 0~3.6 v, 30 pf loading capacitor ) t ds data setup time 5 3 - ns t dh data hold time 0 - - ns t v data output valid time - 13 18 ns figure 8.7 - 1 spi master mode timing diagram symbol parameter min . typ . max . unit spi s lave m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+19 ns spi s lave m ode (vdd = 3 . 0 v ~ 3 . 6 v, 30 pf loading capacitor ) t ds data setup time 0 - - ns c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc126 aug . 08 , 201 8 page 134 of 140 rev 1 .0 4 nuc126 series datasheet t dh data hold time 2*pclk+6 - - ns t v data output valid time - 2*pclk+19 2*pclk+25 ns figure 8.7 - 2 spi slave mode timing diagram c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc126 aug . 08 , 201 8 page 135 of 140 rev 1 .0 4 nuc126 series datasheet 9 package dimensions 9.1 lqfp 100 l ( 14 x 14 x1.4 mm footprint 2.0 mm)
nuc126 aug . 08 , 201 8 page 136 of 140 rev 1 .0 4 nuc126 series datasheet 9.2 lqfp 64l ( 7 x 7 x1.4 mm footprint 2.0 mm)
nuc126 aug . 08 , 201 8 page 137 of 140 rev 1 .0 4 nuc126 series datasheet 9.3 lqfp 48 l (7x7x1.4 mm footprint 2.0 mm) 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
nuc126 aug . 08 , 201 8 page 138 of 140 rev 1 .0 4 nuc126 series datasheet 9.4 qf n 48 l (7x7x 0.8 mm)
nuc126 aug . 08 , 201 8 page 139 of 140 rev 1 .0 4 nuc126 series datasheet 10 revision history date revision description 201 7 . 05 . 05 1 .0 0 1. preliminary v ersion 2017.07.13 1.01 1. revised part number in section 4.1.2 2. revised the range of xin_v ih and xin_v i l in section 8.3.3 2017.09.1 4 1.02 1. r evise d i pwd4 , min si nk current/source current in section 8.2 2. revise d lvr in section 8.4.5 3. revise d bod in section 8.4.6 2017.12.1 5 1.03 1. revise d hirc trim description in section 6.2.8 2. revised clock output description in section 6.3.5 2018.0 8 . 0 8 1.04 1. revised v ddio description in section 1.1 and 4.1.2 . 2. revised timer/pwm pwm mode description in section 2.1 . 3. revised v bat description in section 4.1.2 . 4. added nuc126 qfn48 information in section 2.1 , 4.1 , 4.2 and 9.4 .
nuc126 aug . 08 , 201 8 page 140 of 140 rev 1 .0 4 nuc126 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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